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ARM DS-5 Using the Debug Hardware Configuration Utilities

ARM DS-5 Using the Debug Hardware Configuration Utilities

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Creating debug hardware target configurationsAvailable for all devices, except <strong>the</strong> <strong>ARM</strong>CS-DP, <strong>ARM</strong>JTAG-DP, and<strong>ARM</strong>SW-DP devices.Force ETM power up on connectIf <strong>the</strong> CoreSight ETM (CSETM) is powered down when your debugger attemptsto connection to it, <strong>the</strong>n power up <strong>the</strong> device.Memory Access AP indexThe index number of <strong>the</strong> AHB-AP memory bus on <strong>the</strong> DAP. The AHB-AP bus isused to perform memory operations within <strong>the</strong> CoreSight system.Available for <strong>the</strong> <strong>ARM</strong>CS-DP, <strong>ARM</strong>JTAG-DP, and <strong>ARM</strong>SW-DP devices only.The <strong>ARM</strong>CS-DP device represents <strong>the</strong> <strong>Debug</strong> Access Port (DAP) in a CoreSight system. Thisdevice is automatically detected when you autoconfigure a CoreSight system. However, anydevices connected to <strong>the</strong> DAP are not detected. Therefore, you must read <strong>the</strong> CoreSight ROMtable of <strong>the</strong> <strong>ARM</strong>CS-DP to determine <strong>the</strong> devices that are connected to <strong>the</strong> DAP.The <strong>ARM</strong>11xx-JTAG-AP device represents <strong>the</strong> JTAG-AP in a CoreSight system. To debugCoreSight systems that have processors connected to <strong>the</strong> DAP <strong>the</strong> JTAG-AP, <strong>the</strong> debug unitmust know <strong>the</strong> pre-scan and post-scan bits for JTAG operations.Multiple devices on <strong>the</strong> JTAG scan chain are connected in series, with data flowing serially fromTDI to TDO. This means that debugging a given target in <strong>the</strong> chain requires that certain pre-scanand post-scan bits are used. These bits ensure that <strong>the</strong> o<strong>the</strong>r devices are not affected by <strong>the</strong> datadirected at <strong>the</strong> target device, and that <strong>the</strong> data is positioned correctly in <strong>the</strong> serial scan for <strong>the</strong>target device.5.17.3 See alsoTasks• Configuring CoreSight processors on page 6-22• Configuring <strong>ARM</strong>7, <strong>ARM</strong>9, and <strong>ARM</strong>11 processors in CoreSight systems on page 6-24• Configuring a target processor for virtual E<strong>the</strong>rnet on page 5-51.Concepts• Strategies used by debug hardware to debug cached processors on page 8-15.<strong>ARM</strong> DUI 0498F Copyright © 2010-2012 <strong>ARM</strong>. All rights reserved. 5-32ID021112Non-Confidential

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