ARM DS-5 Using the Debug Hardware Configuration Utilities

Creating debug hardware target configurationsUnwind vector when halt on vector catchThis control is available if you are using an ARM10 processor. It instructs thedebug unit to unwind the vector if you have set a vector catch on a SWI, anUndefined instruction, a Prefetch Abort or a Data abort. Unwinding the vectorsets the PC to the address of the code that caused the exception instead of leavingit at the vector address. The LR and CPSR are restored, and debugger displays thecode at this address. This enables you to more easily examine the code that causedthe exception. If you want to run the exception handling code, you must leave thisoption unchecked.NoteThis option is only activated if a vector catch occurs. If a vector catch is not set,then the exception handler is run as normal.Unwind vector when halt on SWIThis control is available if you are using the following:• a Cortex-A8 or Cortex-R4 processor• ARM1136JFS-JTAG-AP, ARM1156T2FS-JTAG-AP, orARM1176JZF-JTAG-AP device.It instructs debug hardware to unwind the Supervisor Call (SVC) vector if youhave set a vector catch on an SVC. Unwinding the vector sets the PC to theaddress of the code that caused the exception instead of leaving it at the vectoraddress. The LR and CPSR are restored, and your debugger displays the code atthis address. This enables you to more easily examine the code that caused theexception. If you want to run the exception handling code, you must leave thisoption unchecked.NoteThis option is only activated if an SVC vector catch occurs. If an SVC vectorcatch is not set, then the exception handler is run as normal.Use LDM or STM for memory accessThis options controls whether or not to use Load Multiple Instructions (LDM) orStore Multiple Instructions (STM) to access target memory. You might need to setthis option if you have a peripheral that is not fully compatible with the AMBA2.0 standard, as in such cases LDM and STM might not be compatible.Write-Through L2 Cache when in debugThis option is available if you are using an ARM11 processor.Use this option with platforms that have a level 2 cache that interferes with debugoperations. By default it is set to False, but the platform configuration filessupplied for affected platforms set it to True.NoteIf you set this option for other platforms, unexpected behavior might result, andcause errors.ARM DUI 0498F Copyright © 2010-2012 ARM. All rights reserved. 5-30ID021112Non-Confidential