ARM DS-5 Using the Debug Hardware Configuration Utilities
ARM DS-5 Using the Debug Hardware Configuration Utilities
ARM DS-5 Using the Debug Hardware Configuration Utilities
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<strong>Debug</strong>ging with your debug hardware unit8.17 <strong>Debug</strong>ging with a target resetDepending on <strong>the</strong> design of <strong>the</strong> reset circuitry, you might be able to carry out a target reset of<strong>the</strong> board. Two forms of reset are required on <strong>the</strong> board:• A full power-on reset that resets everything on <strong>the</strong> board.• A Reset button that resets your development platform depending on whe<strong>the</strong>r or not it is aCoreSight system:— For non-CoreSight systems, everything on <strong>the</strong> board is reset except <strong>the</strong>EmbeddedICE logic.The EmbeddedICE logic is <strong>the</strong> debug logic in <strong>the</strong> processor.— In a CoreSight system, <strong>the</strong> nSRST (system reset) resets <strong>the</strong> entire design, except for<strong>the</strong> debug subsystem and trace subsystem. This includes <strong>the</strong> debug logic from alldevices, debug and trace bus, access ports, and <strong>Debug</strong> Access Port (DAP).NoteThe Reset button mentioned here must not be confused with <strong>the</strong> RESET button located on<strong>the</strong> debug hardware unit itself.If your target implements a Reset button that drives nTRST in addition to nSRST, <strong>the</strong>n <strong>the</strong>EmbeddedICE logic is reset along with <strong>the</strong> board, and <strong>the</strong> debugger might not be able to regainsynchronization. This design is not recommended.If a vector catch is set on <strong>the</strong> reset vector (or on <strong>the</strong> start address of <strong>the</strong> reset code) and <strong>the</strong>recommended reset circuit is used, when <strong>the</strong> target is reset, it halts on reset as required.8.17.1 See alsoTasks• Post-mortem debugging on page 8-2.Concepts• <strong>Debug</strong>ging from reset on page 8-18• <strong>Debug</strong>ging with a simulated reset on page 8-19• <strong>Debug</strong>ging with a reset register on page 8-20• <strong>Debug</strong>ging systems with ROM at <strong>the</strong> exception vector on page 8-22.ReferenceSetting Up <strong>the</strong> <strong>ARM</strong> <strong>DS</strong>TREAM <strong>Hardware</strong>:• The <strong>DS</strong>TREAM unit on page 2-5.<strong>ARM</strong> <strong>DS</strong>TREAM System and Interface Design Reference:• Chapter 2 <strong>ARM</strong> <strong>DS</strong>TREAM System Design Guidelines.Setting Up <strong>the</strong> <strong>ARM</strong> RVI and RVT <strong>Hardware</strong>:• RVT and RVT2 product contents on page 2-4.<strong>ARM</strong> RVI and RVT System and Interface Design Reference:• Chapter 2 RVI and RVT System Design Guidelines.<strong>ARM</strong> DUI 0498F Copyright © 2010-2012 <strong>ARM</strong>. All rights reserved. 8-21ID021112Non-Confidential
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