ARM DS-5 Using the Debug Hardware Configuration Utilities

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Debugging with your debug hardware unit8.16 Debugging with a reset registerWhere supported, some processors, particularly CoreSight ones such as the Cortex-M3, includea reset register that can reset the processor without using the physical reset lines. In amulti-processor system, this can be used to reset only the target processor and not the completesystem. This type of reset can be selected by setting the reset type to Ctrl_Reg.8.16.1 See alsoTasks• Post-mortem debugging on page 8-2.Concepts• Debugging from reset on page 8-18• Debugging with a simulated reset on page 8-19• Debugging with a target reset on page 8-21• Debugging systems with ROM at the exception vector on page 8-22.ARM DUI 0498F Copyright © 2010-2012 ARM. All rights reserved. 8-20ID021112Non-Confidential
Debugging with your debug hardware unit8.17 Debugging with a target resetDepending on the design of the reset circuitry, you might be able to carry out a target reset ofthe board. Two forms of reset are required on the board:• A full power-on reset that resets everything on the board.• A Reset button that resets your development platform depending on whether or not it is aCoreSight system:— For non-CoreSight systems, everything on the board is reset except theEmbeddedICE logic.The EmbeddedICE logic is the debug logic in the processor.— In a CoreSight system, the nSRST (system reset) resets the entire design, except forthe debug subsystem and trace subsystem. This includes the debug logic from alldevices, debug and trace bus, access ports, and Debug Access Port (DAP).NoteThe Reset button mentioned here must not be confused with the RESET button located onthe debug hardware unit itself.If your target implements a Reset button that drives nTRST in addition to nSRST, then theEmbeddedICE logic is reset along with the board, and the debugger might not be able to regainsynchronization. This design is not recommended.If a vector catch is set on the reset vector (or on the start address of the reset code) and therecommended reset circuit is used, when the target is reset, it halts on reset as required.8.17.1 See alsoTasks• Post-mortem debugging on page 8-2.Concepts• Debugging from reset on page 8-18• Debugging with a simulated reset on page 8-19• Debugging with a reset register on page 8-20• Debugging systems with ROM at the exception vector on page 8-22.ReferenceSetting Up the ARM DSTREAM Hardware:• The DSTREAM unit on page 2-5.ARM DSTREAM System and Interface Design Reference:• Chapter 2 ARM DSTREAM System Design Guidelines.Setting Up the ARM RVI and RVT Hardware:• RVT and RVT2 product contents on page 2-4.ARM RVI and RVT System and Interface Design Reference:• Chapter 2 RVI and RVT System Design Guidelines.ARM DUI 0498F Copyright © 2010-2012 ARM. All rights reserved. 8-21ID021112Non-Confidential
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®ARMDS-5Version 5.9Using the Debug
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Conformance NoticesThis section con
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Contents4.6 Restarting the debug ha
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Contents10.6 Auto Configure button
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Conventions and feedback• the ser
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Getting started with the debug hard
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Chapter 3Configuring network settin
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Configuring network settings for yo
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Managing the firmware on your debug
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Chapter 5Creating debug hardware ta
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Creating debug hardware target conf
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Page 97 and 98: Configuring CoreSight systems6.1 Ab
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Troubleshooting your debug hardware
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ARM DS-5 Using the Debug Hardware Configuration Utilities

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