ARM DS-5 Using the Debug Hardware Configuration Utilities

Debugging with your debug hardware unit8.12 Considerations when debugging processors with caches enabledWhen debugging a processor with caches enabled, you might have to provide the address of anarea of memory on the target that can be used exclusively by debug hardware. On some targets,the debug software downloads code sequences to this area to perform various tasks, such ascleaning the cache, and accessing the system registers. Debug hardware does not preserve thecontents of this area.A code sequence area is only required for certain processors where the required operationscannot be performed directly over JTAG. If debug hardware requires a code sequence area, andone has not been enabled, errors are displayed within the debugger. For example:• Error V28305 (Vehicle): Memory operation failed• Warning: Code sequence memory area size error• Unable to load code sequence into defined memory area.NoteThe code sequence area must be 128 bytes long and in a non-cacheable, readable and writeablearea.To set up a code sequence area, use the options for each specific processor in the DebugHardware Config utility. This provides access to configuration items for each processor for:• enabling code sequences• setting the address and size of the code sequence areas.NoteThese settings might also be available in your debugger Registers view. Any settings modifiedusing the Registers view in your debugger are only modified for the duration of the debugsession. Any settings modified using the Debug Hardware Config utility are persistent untilmodified again.8.12.1 See alsoTasks• Post-mortem debugging on page 8-2.Concepts• Semihosting on page 8-4• Strategies used by debug hardware to debug cached processors on page 8-15• Debugging applications in ROM on page 8-17.ARM DUI 0498F Copyright © 2010-2012 ARM. All rights reserved. 8-16ID021112Non-Confidential