ARM DS-5 Using the Debug Hardware Configuration Utilities
ARM DS-5 Using the Debug Hardware Configuration Utilities
ARM DS-5 Using the Debug Hardware Configuration Utilities
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<strong>Debug</strong>ging with your debug hardware unit8.11 Strategies used by debug hardware to debug cached processorsWhen debugging a cached processor, debug hardware uses <strong>the</strong> following strategies.On debug entry• <strong>Debug</strong> hardware forces Write-Through (WT) on processors that supportthis debug feature.• <strong>Debug</strong> hardware disables cache line fill on processors that supportdisabling of this feature in debug.• <strong>Debug</strong> hardware disables Translation Look-aside Buffer (TLB) loads onprocessors that support disabling of this feature in debug.• If data is read from cacheable memory, it is only read into <strong>the</strong> caches if, andonly if, disable linefill is not possible.• TLB entries and caches remain enabled.On data write• If WT is possible, nothing cache-related is performed.• If WT is not possible, <strong>the</strong> write depends on processor size and data size:1. <strong>Debug</strong> hardware can write to memory with caches enabled, and <strong>the</strong>nwrite disabled, effectively simulating write through.2. <strong>Debug</strong> hardware can clean and invalidate <strong>the</strong> D cache and disable it.NoteThe <strong>ARM</strong>940T processor requires that Code Sequences are enabledto do this.On restart into debug• On processors that support <strong>the</strong> features, forced WT is removed, linefills arere-enabled, and TLB loads are enabled. If, and only if, data has beenwritten, <strong>the</strong> I cache is invalidated. If, and only if, D cache has been disabled,<strong>the</strong>n it is re-enabled.Data writes that could cause <strong>the</strong> cache operations described include user accessesusing your debugger, downloads, and any software breakpoints present in <strong>the</strong>system.NoteFor <strong>the</strong> <strong>ARM</strong>940T processor you must configure <strong>the</strong> code sequence settings before attemptingto debug with caches enabled.When <strong>the</strong> cache is enabled, <strong>the</strong> speed of semihosting decreases, because of <strong>the</strong> additional cachemaintenance overhead performed by <strong>the</strong> debugger.8.11.1 See alsoTasks• Post-mortem debugging on page 8-2.Concepts• Semihosting on page 8-4• <strong>Debug</strong>ging applications in ROM on page 8-17.<strong>ARM</strong> DUI 0498F Copyright © 2010-2012 <strong>ARM</strong>. All rights reserved. 8-15ID021112Non-Confidential
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