ARM DS-5 Using the Debug Hardware Configuration Utilities
ARM DS-5 Using the Debug Hardware Configuration Utilities
ARM DS-5 Using the Debug Hardware Configuration Utilities
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<strong>Debug</strong>ging with your debug hardware unit8.7 Processor exceptionsDepending on implementation options, most <strong>ARM</strong> processors provide dedicated hardware toenter debug state when a predetermined event occurs.Most recent <strong>ARM</strong> processors provide hardware for trapping exceptions. When enabled, <strong>the</strong>effect is similar to placing a breakpoint on <strong>the</strong> selected vector table entry. This is called vectorcatch. However:• Some <strong>ARM</strong> processors, such as <strong>ARM</strong>7, do not provide vector catch hardware. For <strong>the</strong>seprocessors, debug hardware simulates vector catch using instruction breakpoints.• For Cortex-M3, this is equivalent to putting a breakpoint at <strong>the</strong> target of <strong>the</strong> vector.Cortex-M3 has a restricted set of vector catches available.• If <strong>the</strong> exception vectors are in ROM, debug hardware must use hardware breakpoints tosimulate vector catch. This reduces <strong>the</strong> number of resources available for o<strong>the</strong>r purposes,if <strong>the</strong> processor does not have vector catch support.When <strong>the</strong> debug hardware simulates vector catch on earlier <strong>ARM</strong> processors that do not havevector catch support, it uses a software breakpoint when <strong>the</strong> vector table is located in RAM.You must take care when debugging through a system reset. Some hardware targets alter <strong>the</strong>memory map after reset, so <strong>the</strong> location of in physical memory containing software breakpointmight not be in <strong>the</strong> correct reset position. The following warning is output to <strong>the</strong> your debuggerconsole if debug hardware simulates reset vector catch using an instruction breakpoint:Warning: A software breakpoint is being used to simulate reset vector catch.This may fail to be hit if <strong>the</strong> memory is remapped when a reset occurs.The exact behavior of <strong>the</strong> <strong>ARM</strong> vector catch hardware depends on <strong>the</strong> processor. <strong>ARM</strong>9processors enter debug state only when <strong>the</strong> specified exception occurs. O<strong>the</strong>r processors, suchas <strong>ARM</strong>11 or older processors that use a breakpoint, enter debug state whenever <strong>the</strong> instructionat <strong>the</strong> exception vector is executed, regardless of whe<strong>the</strong>r <strong>the</strong> exception occurs or not.8.7.1 See alsoConcepts• <strong>Hardware</strong> breakpoints on page 8-8• Software instruction breakpoints on page 8-9• Breakpoints and <strong>the</strong> program counter on page 8-11• Interaction between breakpoint handling in <strong>the</strong> debug hardware and your debugger onpage 8-12• Problems setting breakpoints on page 8-14.<strong>ARM</strong> DUI 0498F Copyright © 2010-2012 <strong>ARM</strong>. All rights reserved. 8-10ID021112Non-Confidential