ARM DS-5 Using the Debug Hardware Configuration Utilities

Debugging with your debug hardware unit8.4 Cortex-M3 semihostingBecause Cortex-M3 does not provide vector catch on SVC, and the vector table contains jumpaddresses rather than instructions, semihosting cannot be supported using an SVC instruction.As an alternative, semihosting is implemented using a specific software breakpoint that isrecognized as a semihosting break by the debugger. The breakpoint instruction opcode containsan immediate 8-bit value. The C library uses the BKPT 0xAB opcode for semihosting. Thedebugger can test for this opcode pattern to determine if the breakpoint was a semihostingrequest or not.When the semihosting break is executed, the semihosting call is processed in the normal way.After processing, execution continues from the instruction that follows the software breakpoint.The debugger does not stop on the breakpoint.8.4.1 See alsoTasks• Adding an application SVC handler when using debug hardware on page 8-5.ARM DUI 0498F Copyright © 2010-2012 ARM. All rights reserved. 8-7ID021112Non-Confidential