ARM DS-5 Using the Debug Hardware Configuration Utilities
ARM DS-5 Using the Debug Hardware Configuration Utilities
ARM DS-5 Using the Debug Hardware Configuration Utilities
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Configuring CoreSight systems6.14 CoreSight topology and associations for multiple trace sourcesThe following figure shows <strong>the</strong>re are two Cortex-R4 processors in <strong>the</strong> system, each with anassociated ETM:FunnelReplicatorCortex-R4 #1 CSETM #1TPIUCortex-R4 #2 CSETM #2ETBAPBAPB-APDAP<strong>ARM</strong>CS-DPFigure 6-13 CoreSight system topology diagram - multiple trace source systemThe processors and ETMs are numbered for convenience, and this numbering scheme is used in<strong>the</strong> Associations file.The Association file for this is:Name=<strong>ARM</strong>CS-DP;Type=<strong>ARM</strong>CS-DP; Name=Cortex-R4_1;Type=Cortex-R4;ETM=CSETM_1;Name=Cortex-R4_2;Type=Cortex-R4;ETM=CSETM_2;Name=CSETM_1;Type=CSETM;TraceOutput0=TPIU;TraceOutput1=ETB;Core=Cortex-R4_1;Name=CSETM_2;Type=CSETM;TraceOutput0=TPIU;TraceOutput1=ETB;Core=Cortex-R4_2;Name=Funnel;Type=CSTFunnel; Name=ETB;Type=CSETB;Port0=CSETM_1;Port1=CSETM_2;Name=TPIU;Type=CSTPIU;Port0=CSETM_1;Port1=CSETM_2;6.14.1 See alsoConcepts• About trace associations on page 6-6• Defining CoreSight trace associations on page 6-7• CoreSight topology and associations for <strong>the</strong> CoreSight DK11 on page 6-15• CoreSight topology and associations for <strong>the</strong> Cortex-R4 FPGA on page 6-17• CoreSight topology and associations for <strong>the</strong> Cortex-M3 FPGA on page 6-19.Reference• CoreSight device names and classes on page 5-52• Format of trace associations on page 6-8• Trace Association Editor dialog box on page 6-9.<strong>ARM</strong> DUI 0498F Copyright © 2010-2012 <strong>ARM</strong>. All rights reserved. 6-21ID021112Non-Confidential
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