ARM DS-5 Using the Debug Hardware Configuration Utilities

Configuring CoreSight systems6.13 CoreSight topology and associations for the Cortex-M3 FPGAThe following figure shows the CoreSight topology diagram for Cortex-M3 FPGA:TraceFunnelCortex-M3CSETMTPIUAHBAHB-APDAPARMCS-DPThe Association file for this is:Figure 6-12 CoreSight system topology diagram - Cortex-M3 FPGAName=ARMCS-DP;Type=ARMCS-DP;Name=Cortex-M3;Type=Cortex-M3;ETM=ETMM3;Name=ETMM3;Type=CSETM;Core=Cortex-M3;TraceOutput=TPIU;Name=Funnel;Type=CSTFunnel;Name=TPIU;Type=CSTPIU;Port0=ETMM3;In this Association file:Name=ARMCS-DP;Type=ARMCS-DP;This line specifies the first device in our list is the ARM CoreSight Debug port.Any CoreSight components that are connected using the Debug Port associatedwith this template must follow this device.Name=Cortex-M3;Type=Cortex-M3;ETM=ETMM3;This line specifies that a Cortex-M3 processor is accessible using the precedingARMCS-DP. The ETM=ETMM3 section states that the processor has an associatedETM called ETMM3.Name=ETMM3;Type=CSETM;Core=Cortex-M3;TraceOutput=TPIU;This line specifies that an ETM is accessible using the preceding ARMCS-DP.TraceOutput=TPIU signifies that this ETM can output into the component namedTrace Port Interface Unit (TPIU).Core=Cortex-M3 signifies that the source for trace captured by this ETM is theCortex-M3 device.Name=Funnel;Type=CSTFunnel;This line specifies that a CoreSight Trace Funnel is accessible using the precedingARMCS-DP.Name=TPIU;Type=CSTPIU;Port0=ETMM3;This line specifies that a CoreSight TPIU is accessible using the precedingARMCS_DP.Port0=ETMM3 indicates that the source of trace that is stored in this ETB is thecomponent named ETMM3.ARM DUI 0498F Copyright © 2010-2012 ARM. All rights reserved. 6-19ID021112Non-Confidential