ARM DS-5 Using the Debug Hardware Configuration Utilities

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Configuring CoreSight systems6.12 CoreSight topology and associations for the Cortex-R4 FPGAThe following figure shows the CoreSight topology diagram for Cortex-R4 FPGA:TPIUCortex-R4CSETMETBAPBAPB-APDAPARMCS-DPThe Association file for this is:Figure 6-10 CoreSight system topology diagram - Cortex-R4 FPGAName=ARMCS-DP;Type=ARMCS-DP;Name=Cortex-R4;Type=Cortex-R4;ETM=ETMR4;Name=ETMR4;Type=CSETM;TraceOutput0=TPIU;TraceOutput1=ETB;Core=Cortex-R4;Name=ETB;Type=CSETB;Port0=ETMR4;Name=TPIU;Type=CSTPIU;Port0=ETMR4;In this Association file:Name=ARMCS-DP;Type=ARMCS-DP;This line specifies the first device in our list is the ARM CoreSight Debug port.Any CoreSight components that are connected using the Debug Port associatedwith this template must follow this device.Name=Cortex-R4;Type=Cortex-R4;ETM=ETMR4;This line specifies that a Cortex-R4 processor is connected using the precedingARMCS-DP. The ETM=ETMR4 section states that the processor has an associatedETM called ETMR4.Name=ETMR4;Type=CSETM;TraceOutput0=TPIU;TraceOutput1=ETB;Core=Cortex-R4;This line specifies that an ETM is accessible using the preceding ARMCS-DP.TraceOutput0=TPIU signifies that this ETM can output into the component namedTrace Port Interface Unit (TPIU).TraceOutput1=ETB signifies that this ETM can output into the component namedETB.Core=Cortex-R4 signifies that the source for trace captured by this ETM is theCortex-R4 device.Name=ETB;Type=CSETB;Port0=ETMR4;This line specifies that a CoreSight ETB is accessible using the precedingARMCS-DP.Port0=ETMR4; indicates that the source of trace that is stored in this ETB is thecomponent named ETMR4.ARM DUI 0498F Copyright © 2010-2012 ARM. All rights reserved. 6-17ID021112Non-Confidential
Configuring CoreSight systemsName=TPIU;Type=CSTPIU;Port0=ETMR4;This line specifies that a CoreSight TPIU is accessible using the precedingARMCS_DP.Port0=ETMR4; indicates that the source of trace that is routed through this TPIU isthe component named ETMR4.The following figure shows the Cortex-R4 FPGA Associations:1DeviceListARMCS-DPCortex-R4ETMETBTPIU3245671. Associations defined by order of devices2. Association defined by ETM=ETM element for Cortex-R45. Association defined by TraceInput=ETM6. Association defined by TraceInput=ETM3. Association defined by Core=Cortex-R4 7. Association defined by TraceOutput1=TPIU4. Association defined by TraceOutput2=ETBFigure 6-11 Cortex-R4 FPGA Associations6.12.1 See alsoConcepts• Setting up a CoreSight trace association file on page 6-11• About trace associations on page 6-6• Defining CoreSight trace associations on page 6-7• CoreSight topology and associations for the CoreSight DK11 on page 6-15• CoreSight topology and associations for the Cortex-M3 FPGA on page 6-19• CoreSight topology and associations for multiple trace sources on page 6-21.Reference• CoreSight device names and classes on page 5-52• Format of trace associations on page 6-8• Trace Association Editor dialog box on page 6-9.ARM DUI 0498F Copyright © 2010-2012 ARM. All rights reserved. 6-18ID021112Non-Confidential
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®ARMDS-5Version 5.9Using the Debug
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Conformance NoticesThis section con
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Contents4.6 Restarting the debug ha
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Contents10.6 Auto Configure button
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Conventions and feedback• the ser
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Getting started with the debug hard
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Chapter 3Configuring network settin
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Configuring network settings for yo
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Managing the firmware on your debug
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Chapter 5Creating debug hardware ta
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Creating debug hardware target conf
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Page 127 and 128: Using TraceConcepts• About using
Page 129 and 130: Chapter 8Debugging with your debug
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Page 151 and 152: Chapter 9Configuring debug hardware
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Configuring debug hardware for GDB9
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Configuring debug hardware for GDBO
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Configuring debug hardware for GDBR
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Configuring debug hardware for GDB
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Chapter 10Troubleshooting your debu
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Troubleshooting your debug hardware
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ARM DS-5 Using the Debug Hardware Configuration Utilities

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