ModelSim SE GUI Reference - Parent Directory

Indexvalues ofdisplaying in Objects window GR-182examining CR-160forcing anywhere in the hierarchy UM-100,UM-391, UM-403replacing with text CR-350saving as binary log file UM-238waveforms, viewing GR-209Signals (Objects) window UM-292simulatingbatch mode UM-27command-line mode UM-27Comparing simulations UM-237default run length GR-95delays, specifying time units for CR-17design unit, specifying CR-372elaboration file UM-83, UM-140graphic interface to GR-85iteration limit GR-95mixed language designscompilers UM-199libraries UM-199resolution limit in UM-200mixed Verilog and SystemC designschannel and port type mapping UM-205SystemC sc_signal data type mapping UM-206Verilog port direction UM-208Verilog state mapping UM-208mixed Verilog and VHDL designsVerilog parameters UM-202Verilog state mapping UM-203VHDL and Verilog ports UM-202VHDL generics UM-204mixed VHDL and SystemC designsSystemC state mapping UM-213VHDL port direction UM-212VHDL port type mapping UM-210VHDL sc_signal data type mapping UM-210ncsim style CR-233one step CR-233saving dataflow display as a Postscript file UM-310saving options in a project UM-48saving simulations CR-182, CR-381, UM-237saving waveform as a Postscript file UM-277speeding-up with the Profiler UM-363stepping through a simulation CR-265stimulus, applying to signals and nets GR-184stopping simulation in batch mode CR-409SystemC UM-163, UM-178usage flow for SystemC only UM-168time resolution GR-86Verilog UM-131delay modes UM-148hazard detection UM-137optimizing performance UM-77, UM-127resolution limit UM-131XL compatible simulator options UM-138VHDL UM-79viewing results in List pane GR-149viewing results in List window UM-257VITAL packages UM-98simulating the design, overview UM-26simulationbasic steps for UM-24Simulation Configurationcreating UM-48dialog GR-54simulation farmsJobSpy UM-408jobspy CR-177simulation task overview UM-23simulationsevent order in UM-134saving results CR-141, CR-142, UM-237saving results at intervals UM-246saving with checkpoint UM-87, UM-144simulator resolutionmixed designs UM-200returning as a real UM-99SystemC UM-179Verilog UM-131VHDL UM-79vsim -t argument CR-379simulator state variables UM-520simulator version CR-380, CR-391simulator, difference from OSCI UM-188simultaneous events in Verilogchanging order CR-354, CR-366sizetf callback function UM-568sm_entity UM-601SmartModelscreating foreign architectures with sm_entity UM-601invoking SmartModel specific commands UM-604linking to UM-600lmcwin commands UM-605memory arrays UM-606Verilog interface UM-607VHDL interface UM-600so, shared object fileloading PLI/VPI C applications UM-549loading PLI/VPI C++ applications UM-555