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GSC Sentinel-2 PDGS STBD - emits - ESA

GSC Sentinel-2 PDGS STBD - emits - ESA

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<strong>GSC</strong> <strong>Sentinel</strong>-2 <strong>PDGS</strong> <strong>STBD</strong>Issue 1 Revision 2 (draft) - 25.07.2010GMES-GSEG-EOPG-TN-09-0031page 20 of 60This implies that the IPF components are bounded out of a logical decomposition of theprocessing which maximises the parallelisation opportunities of every individual componentwithin the workflow.This first-level parallelisation will hereafter be referred to as “outer parallelisation” allowingseveral instances of the same IPF component (or sequence of IPF components) to runindependently and in parallel onto distinct hardware (e.g. each one processing a differentportion of the input data). This implies the definition of independent “processing-units” (e.g.by fragmenting the input-data), and to allocate each processing unit to an IPF component orsequence of components as illustrated on Figure 5.Figure 5: IPF Outer ParallelisationIn this example, the data to be processed is divided into several independent processingunits that go through a given processing flow in parallel, step by step, each unit-processinggenerating at its term distinct product items. In this mode of operation, it is up to thesupervision subsystem (DPC) to split the input data stream, and to trigger and manageindependent processing instances in parallel on each fragment.In complement, a second level of parallelisation may be applied to some specific IPFcomponents with “inner-parallelisation” techniques. In this case, the IPF component will itselftake advantage of multi-core/multi-CPU target hardware to implement its own workflow (e.g.using MPI programming techniques) as illustrated on Figure 6.<strong>ESA</strong> UNCLASSIFIED – For Official Use© <strong>ESA</strong>The copyright of this document is the property of <strong>ESA</strong>. It is supplied in confidence and shall not be reproduced, copied orcommunicated to any third party without written permission from <strong>ESA</strong>.

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