TECHNICAL MANUAL FOR COMPACT VHF DSC RM2042

5 CIRCUIT DESCRIPTION AND SCHEMATIC DIAGRAMS RM20425.2 MICROPROCESSOR (MODULE 2) PART NO. 626942The microprocessor module contains a micro computer, build round a general purpose microprocessorwith its basic external control logic, memory banks and timers. Furthermore the microprocessor modulecontains a syncronus receiver, and three 8 bit ports.MICROPROCESSOR UNITThe microprocessor unit U6 is a 16 bit MC68HC000 general purpose microprocessor.8.000 MHz OSCILLATORThe 8 MHz oscillator is build as a gate oscillator round U16, with the crystal X1 to control the oscillationfrequency. The output is used as clock input to the microprocessor U6.CONTROL LOGICThe control logic consist of three major blocks. A reset circuit, a DTACK and VPA generator, and interruptcontrol logic.The reset circuit build round U13.3 is used to insure correct initialization of the microprocessor duringpower-on. The microprocessors RESET and HALT inputs must be kept at a logical low level for at least100 ms, after Vcc has reached 5V. If this fails the microprocessor goes into a double bus fault state andhalts (HALT pin is low while RESET is high). R3 and C14 determines the power-on reset time constant.The microprocessor uses an asyncronus databus to communicate with all peripherals. This means thatthe peripherals have to supply the data acknowledge signal (DTACK) to the microprocessor in order totell when they have finished reading the databus, or when data placed on the bus by the peripherals isvalid. If a peripheral does not assert the DTACK signal, the microprocessor will continue to insert waitstates,or ultimately issue a bus error and halt the system.The used memory and peripheral devices do not have an acknowledge signal. The DTACK is insteadgenerated by the binary counter U14, controlled by the 8 MHz clock and the upper and lower data strobes(UDS and LDS) on the microprocessor. When U14-CT1 is used as output, the microprocessor inserts 1wait-state in each read/write cycle. This means that the maximum access time for the memory chips andperipheral devices are 250 ns.One device, i.e. the LCD dot-matrix display, uses a 1 U s bus cycle which is equivalent to the bus cycle usedby M6800 devices. The M6800 bus cycle is supported by the MC68HC000 microprocessor if the VPA(valid peripheral address) signal is asserted instead of the DTACK signal. This is done each time thedisplay is accessed, by gating output no. 7 on U24, i.e. the displays chip select, back to the VPA inputon the microprocessor (via U10.5, U9.3 and U10.1), and at the same time use it to inhibit the generationof DTACK (U9.4, pin 12 is at a logic high level).The interrupt logic consists of U17 that encodes the interrupts, and U23 that clears the presently servedinterrupt. A logical low input to U17 indicates that an interrupt needs to be served. The microprocessorsinterrupt decoder is level sensitive, but inputs to U17 is latched on D-type Flip-Flops, in order to make theinterrupts from the peripheral devices edge triggered instead of level triggered.The interrupt source, i.e. the D-type Flip-Flop that has latched the interrupt signal, is cleared during aninterrupt acknowledge cycle. The interrupt acknowledge cycle is recognized when the microprocessorsfunction code outputs (FC0 - FC3) are high. In order to tell the microprocessor that the interruptacknowledge cycle has been recognized, the VPA signal must be asserted. An interrupt acknowledgecycle is under execution when output from U11.2 is high, this output is gated to the microprocessor in orderto assert VPA.9716PAGE 5-7