VLSI/FPGA Design and Test CAD Tool Flow in Mentor Graphics

VLSI/FPGA
Design and Test CAD Tool
Flow in Mentor Graphics
Victor P. Nelson

or….
“Nightmare on
CAD Tool Street”

Mentor Graphics CAD Tool Suites
�� IC/SoC IC/ SoC design flow
�� DFT design flow
�� FPGA design flow
�� PCB design flow
�� HDL digital modeling & simulation
�� Analog/mixed-signal Analog/mixed signal modeling & simulation
�� ASIC/FPGA synthesis
�� Vendor-provided Vendor provided (Xilinx,Altera,etc
( Xilinx,Altera,etc.) .) back end tools

Auburn “user-setup” “user setup” Options
(select “eda “ eda” ” – Electronic Design Automation)
�� ICFlow2004.3 (2001, (2001, 2005.1) 2005.1)
– ICFlow tools (Design (Design Architect--IC, Architect IC, IC IC Station, Station, Calibre)) Calibre
– Simulation tools ((Modelsim Modelsim, , ADVance ADVance MS, MS, Eldo)) Eldo
– Synthesis (Leonardo) (Leonardo)
– DFT tools (DFT (DFT Advisor, Advisor, Flextest, Flextest,
Fastscan)) Fastscan
– Limited access to Quicksim II (some (some technologies)
technologies)
�� EN2002u3 (EN2001) (EN2001)
– Design Architect, Quicksim II,Quicksim Pro (Front (Front End) End)
– ModelSim & Leonardo (Simulation/Synthesis)
– Xilinx/Altera tools (Back (Back End) End)
FPGA (FPGA (FPGA Advantage, Advantage, Modelsim, Modelsim,
Leonardo)
Leonardo)
�� FPGA

Mentor Graphics
Front-End Tools
(Technology-Independent)
Xilinx/Altera/Other
Back-End Tools
(Technology-Specific)
FPGA Design Flow
Behavioral
Design
Synthesis
Gate-Level
Schematic
Map, Place
& Route
EDIF Netlist
FPGA Configuration File
Verify
Function
Verify
Function
Verify
Timing

DFT/BIST
& ATPG
DRC & LVS
Verification
IC/ASIC Design Flow
Behavioral
Design
Gate-Level
Netlist
Transistor-Level
Netlist
Physical
Layout
Mask Data
Verify
Function
Verify
Function
Verify Function
& Timing
Verify
Timing

Mentor Graphics
ASIC Design Kit 3.0
�� Technology files (all) & standard cell libraries (exc. tsmc018)
– ami12, ami05 (AMI 1.2um, 0.5um)
– tsmc035, tsmc025, tsmc018 (TSMC 0.35um, 0.25um, 0.18um)
�� Support for IC Flow & DFT tools:
– Synthesis ((LeonardoSpectrum
LeonardoSpectrum))
– Schematic capture (Design (Design Architect--IC)
Architect IC)
– Design for test & ATPG (DFT (DFT Advisor, Advisor, Flextest/Fastscan))
Flextest/Fastscan
– Simulation
�� Modelsim/ADVance MS: MS:
VHDL/Verilog/Mixed-Signal VHDL/Verilog/Mixed Signal models
�� Eldo/Accusim Eldo/Accusim analog (SPICE) models
�� Mach Mach TA TA post-layout post layout timing
�� Quicksim Quicksim II, II, Quicksim Quicksim Pro Pro (except tsmc025,tsmc018)
– IC layout & verification (standard cell & custom)
�� IC IC Station Station
�� Calibre, Calibre,
SST SST Velocity
Velocity

Behavioral Design & Verification
VHDL
Verilog
SystemC
(mostly technology-independent)
technology independent)
ModelSim
(digital)
Leonardo
Spectrum
(digital)
Create Behavioral/RTL
HDL Model(s)
Simulate to Verify
Functionality
Synthesize Gate-Level
Circuit
Technology-Specific Netlist
to Back-End Tools
VHDL-AMS
Verilog-A
ADVance MS
(analog/mixed signal)
Technology Libraries

Digital HDL Simulation
Working
Library
Simulation
Setup
VHDL,Verilog
Models
Design_1
Design_2
Result
Waveforms
ModelSim
VITAL
IEEE 1164
Result
Listing
Resource
Libraries
Input
Stimuli

Mixed-Signal Mixed Signal HDL Simulation
Analog
(SPICE)
Working
Library
Simulation
Setup
Eldo,
Eldo RF
VHDL,Verilog,
VHDL-AMS, Verilog-A,
SPICE Models
Mach TA
Design_1
Design_2
VITAL
ADVance MS
EZwave
or Xelga
View Results
IEEE 1164
Resource
Libraries
Input
Stimuli
ModelSim
Digital
(VHDL,Verilog)

ADVance MS Simulation System
�� ADVance MS “kernel” supports:
– VHDL & Verilog: digital (via ModelSim) ModelSim
– VHDL-AMS VHDL AMS & Verilog-A: Verilog A: analog/mixed signal
– Eldo/SPICE: Eldo/SPICE:
analog (via Eldo) Eldo
– Eldo RF/SPICE: analog RF (via Eldo RF)
– Mach TA/SPICE: high-speed high speed analog/timing
�� Invoke stand-alone stand alone or from Design Architect-IC
Architect IC
�� Mentor Graphics “Legacy” Simulators (PCB design)
– Quicksim II, Quicksim Pro (digital)
– ASIC: adk_quicksim
adk_quicksim
– FPGA/PLD: Xilinx: pld_quicksim, pld_quicksim,
Altera: max2_quicksim
– Accusim (analog): adk_accusim
adk_accusim

Technology
Synthesis
Libraries
FPGA
ASIC
Automated Synthesis
HDL Behavioral/RTL Models
Leonardo Spectrum
(Level 3)
Technology-
Specific
Netlist
VHDL, Verilog, SDF,
EDIF, XNF
Design
Constraints
Level 1 – FPGA
Level 2 – FPGA + Timing

Leonardo – ASIC Synthesis Flow

Synthesis Example
�� Load technology library:
tsmc035 (ASIC), or Xilinx Spartan2 (FPGA)
�� Load design file: seqckt.vhd
�� Specify constraints: clock freq, delays, etc.
�� Optimization: effort, performance vs. area
�� Write synthesized netlist output(s): output(s):
– seqckt_0.vhd : VHDL netlist for ModelSim & DFT
– seqckt.v : Verilog netlist for import into DA-IC DA IC
– seqckt.sdf : For ModelSim to study timing
– seqckt.edf : EDIF netlist for 3 rd party tools
– seqckt.xnf : Xilinx netlist for Xilinx ISE

Mentor Graphics DFT Design Flow
Memory
& Logic
BIST Boundary
Scan
Internal
Scan Design
ATPG

VHDL/Verilog
Netlist With
Scan Elements
ASIC DFT Flow
DFT Advisor
Synthesized VHDL/Verilog Netlist
Fastscan/
Flextest
Insert Internal
Scan Circuitry
Generate/Verify
Test Vectors
Test Pattern File
ATPG Library
adk.atpg

Xilinx “ISE”
Altera “Max Plus 2”
Physical Design - FPGA
User-Specified
Constraints
Component-Level Netlist
Generate
Programming
Data
Configuration File
Map to FPGA
LUTs, FFs, IOBs
Place & Route
Generate
Timing Model
Simulation Model
FPGA/PLD
Technology
Files

Physical Design – ASIC (Std. Cell)
Std. Cell
Layouts
Process Data
Design Rules
Design Rule
Check
Component-Level Netlist
Generate
Mask Data
IC Mask Data
Floorplan
Chip/Block
Place & Route
Std. Cells
Backannotate
Schematic
Mentor Graphics
“IC Station”
Layout vs.
Schematic
Check
Mach TA/Eldo Simulation Model

Design Architect-IC Architect IC Design Flow

Preparation for Layout
�� Convert Verilog netlist to Mentor Graphics
“EDDM” netlist format
– Invoke Design Architect-IC
Architect IC ((adk_daic adk_daic))
– “Import Verilog” feature to create schematic
�� mapping file $ADK/technology/adk_map.vmp
$ADK/technology/ adk_map.vmp
– Open the generated schematic
– Prepare “design viewpoints” for layout
�� May also create schematic diagrams for “hand-
designed” circuits – gate and/or transistor level
– Components from ADK library