PIC12(L)F1501 Data Sheet - Microchip

PIC12(L)F1501Data Sheet8-Pin Flash, 8-Bit Microcontrollers*8-bit, 8-pin devices protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. andforeign patents and applications may be issued or pending. 2011 Microchip Technology Inc. Preliminary DS41615A

8-Pin Flash, 8-Bit MicrocontrollersPIC12(L)F1501High-Performance RISC CPU:• C Compiler Optimized Architecture• Only 49 Instructions• 1K Words Linear Program Memory Addressing• 64 bytes Linear Data Memory Addressing• Operating Speed:- DC – 20 MHz clock input- DC – 200 ns instruction cycle• Interrupt Capability with Automatic ContextSaving• 16-Level Deep Hardware Stack with OptionalOverflow/Underflow Reset• Direct, Indirect and Relative Addressing modes:- Two full 16-bit File Select Registers (FSRs)- FSRs can read program and data memoryFlexible Oscillator Structure:• 16 MHz Internal Oscillator Block:- Factory calibrated to ±1%, typical- Software selectable frequency range from16 MHz to 31 kHz• 31 kHz Low-Power Internal Oscillator• Three External Clock modes up to 20 MHzSpecial Microcontroller Features:• Operating Voltage Range:- 1.8V to 3.6V (PIC12LF1501)- 2.3V to 5.5V (PIC12F1501)• Self-Programmable under Software Control• Power-on Reset (POR)• Power-up Timer (PWRT)• Programmable Low-Power Brown-Out Reset(LPBOR)• Extended Watchdog Timer (WDT):- Programmable period from 1 ms to 256s• Programmable Code Protection• In-Circuit Serial Programming (ICSP) via TwoPins• Enhanced Low-Voltage Programming (LVP)• Power-Saving Sleep mode:- Low-Power Sleep mode- Low-Power BOR (LPBOR)• Integrated Temperature Indicator• 128 Bytes High-Endurance Flash:- 100,000 write Flash endurance (minimum)Low-Power Features (PIC12LF1501):• Standby Current:- 20 nA @ 1.8V, typical• Watchdog Timer Current:- 200 nA @ 1.8V, typical• Operating Current:- 30 A/MHz @ 1.8V, typicalPeripheral Features:• Analog-to-Digital Converter (ADC):- 10-bit resolution- 4 external channels- 2 internal channels:- Fixed Voltage Reference and DAC channels- Temperature Indicator channel- Auto acquisition capability- Conversion available during Sleep• 1 Comparator:- Rail-to-rail inputs- Power mode control- Software controllable hysteresis• Voltage Reference module:- Fixed Voltage Reference (FVR) with 1.024V,2.048V and 4.096V output levels- 1 rail-to-rail resistive 5-bit DAC with positivereference selection• 6 I/O Pins (1 Input-only Pin):- High current sink/source 25 mA/25 mA- Individually programmable weak pull-ups- Individually programmable interrupt-on-change(IOC) pins• Timer0: 8-Bit Timer/Counter with 8-BitProgrammable Prescaler• Enhanced Timer1:- 16-bit timer/counter with prescaler- External Gate Input mode• Timer2: 8-Bit Timer/Counter with 8-Bit PeriodRegister, Prescaler and Postscaler• Four 10-bit PWM modules• 2 Configurable Logic Cell (CLC) modules:- 16 selectable input source signals- Four inputs per module- Software control of combinational/sequentiallogic/state/clock functions- AND/OR/XOR/D Flop/D Latch/SR/JK- External or internal inputs/outputs- Operation while in Sleep 2011 Microchip Technology Inc. Preliminary DS41615A-page 3

PIC12(L)F1501Peripheral Features (Continued):• Numerically Controlled Oscillator (NCO):- 20-bit accumulator- 16-bit increment- True linear frequency control- High-speed clock input- Selectable Output modes:- Fixed Duty Cycle (FDC) mode- Pulse Frequency (PF) mode• Complementary Waveform Generator (CWG):- 8 selectable signal sources- Selectable falling and rising edge dead-bandcontrol- Polarity control- 4 auto-shutdown sources- Multiple input sources: PWM, CLC, NCOPIC12(L)F1501/PIC16(L)F150X Family TypesDeviceData Sheet IndexProgram MemoryFlash (words)Data SRAM(bytes)I/O’s (2)10-bit ADC (ch)ComparatorsDACTimers(8/16-bit)PIC12(L)F1501 (1) 1024 64 6 4 1 1 2/1 4 — — 1 2 1 H —PIC16(L)F1503 (2) 2048 128 12 8 2 1 2/1 4 — 1 1 2 1 H —PIC16(L)F1507 (3) 2048 128 18 12 — — 2/1 4 — — 1 2 1 H —PIC16(L)F1508 (4) 4096 256 18 12 2 1 2/1 4 1 1 1 4 1 I/H YPIC16(L)F1509 (4) 8192 512 18 12 2 1 2/1 4 1 1 1 4 1 I/H YNote 1: I - Debugging, Integrated on Chip; H - Debugging, Requires Debug Header.2: One pin is input-only.Data Sheet Index: (Unshaded devices are described in this document.)1: Future Product PIC12(L)F1501 Data Sheet, 8-Pin Flash, 8-bit Microcontrollers.2: DS41607 PIC16(L)F1503 Data Sheet, 14-Pin Flash, 8-bit Microcontrollers.3: DS41586 PIC16(L)F1507 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers.4: DS41609 PIC16(L)F1508/1509 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers.PWMEUSARTMSSP (I 2 C/SPI)CWGCLCNCODebug (1)XLPDS41615A-page 4 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501FIGURE 1:8-PIN PDIP, SOIC, MSOP, DFN DIAGRAM FOR PIC12(L)F1501PDIP, SOIC, MSOP, DFNVDD18VSSRA5RA4MCLR/VPP/RA3234765Note:See Table 1 for location of all peripheral functions.TABLE 1:8-PIN ALLOCATION TABLE (PIC12(L)F1501)I/O8-Pin PDIP/SOIC/MSOP/DFNADCReferenceComparatorTimerCWGNCOCLCPWMInterruptPull-UpBasicPIC12(L)F1501RA0/ICSPDATRA1/ICSPCLKRA2RA0 7 AN0 DACOUT1 C1IN+ — CWG1B (1) — CLC2IN1 PWM2 IOC Y ICSPDATRA1 6 AN1 VREF+ C1IN0- — — NCO1 (1) CLC2IN0 — IOC Y ICSPCLKRA2 5 AN2 DACOUT2 C1OUT T0CKI CWG1A (1) — CLC1 (1) PWM1 INT Y —CWG1FLTIOCRA3 4 — — — T1G (2) — — CLC1IN0 — IOC Y MCLRVPPRA4 3 AN3 — C1IN1- T1G (1) CWG1B (2) CLC1 (2) PWM3 IOC Y CLKOUTRA5 2 — — — T1CKI CWG1A (2) NCO1 (2)NCO1CLKCLC1IN1CLC2PWM4 IOC Y CLKINVDD 1 — — — — — — — — — — VDDVSS 8 — — — — — — — — — — VSSNote 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.2: Alternate location for peripheral pin function selected by the APFCON register. 2011 Microchip Technology Inc. Preliminary DS41615A-page 5

PIC12(L)F1501Table of Contents1.0 Device Overview .......................................................................................................................................................................... 92.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 133.0 Memory Organization ................................................................................................................................................................. 154.0 Device Configuration .................................................................................................................................................................. 395.0 Oscillator Module........................................................................................................................................................................ 456.0 Resets ........................................................................................................................................................................................ 537.0 Interrupts .................................................................................................................................................................................... 618.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 759.0 Watchdog Timer ......................................................................................................................................................................... 7910.0 Flash Program Memory Control ................................................................................................................................................. 8311.0 I/O Ports ..................................................................................................................................................................................... 9912.0 Interrupt-On-Change ................................................................................................................................................................ 10513.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 10914.0 Temperature Indicator Module ................................................................................................................................................. 11115.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 11316.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 12717.0 Comparator Module.................................................................................................................................................................. 13118.0 Timer0 Module ......................................................................................................................................................................... 14119.0 Timer1 Module with Gate Control............................................................................................................................................. 14520.0 Timer2 Module ......................................................................................................................................................................... 15721.0 Pulse-Width Modulation (PWM) Module .................................................................................................................................. 16122.0 Configurable Logic Cell (CLC).................................................................................................................................................. 16723.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 18324.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 19325.0 In-Circuit Serial Programming (ICSP) ............................................................................................................................... 20926.0 Instruction Set Summary .......................................................................................................................................................... 21127.0 Electrical Specifications............................................................................................................................................................ 22528.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 24729.0 Development Support............................................................................................................................................................... 24930.0 Packaging Information.............................................................................................................................................................. 253Appendix A: Data Sheet Revision History.......................................................................................................................................... 267Index .................................................................................................................................................................................................. 269The Microchip Web Site ..................................................................................................................................................................... 275Customer Change Notification Service .............................................................................................................................................. 275Customer Support .............................................................................................................................................................................. 275Reader Response .............................................................................................................................................................................. 276Product Identification System............................................................................................................................................................. 277DS41615A-page 6 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced.If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. Wewelcome your feedback.Most Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:http://www.microchip.comYou can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following:• Microchip’s Worldwide Web site; http://www.microchip.com• Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you areusing.Customer Notification SystemRegister on our web site at www.microchip.com to receive the most current information on all of our products. 2011 Microchip Technology Inc. Preliminary DS41615A-page 7

PIC12(L)F1501NOTES:DS41615A-page 8 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15011.0 DEVICE OVERVIEWThe PIC12(L)F1501 are described within this data sheet.They are available in 14-pin packages. Figure 1-1 showsa block diagram of the PIC12(L)F1501 devices. Table 1-2shows the pinout descriptions.Reference Table 1-1 for peripherals available perdevice.TABLE 1-1:PeripheralDEVICE PERIPHERALSUMMARYPIC12F1501PIC12LF1501Analog-to-Digital Converter (ADC) ● ●Complementary Wave Generator (CWG) ● ●Digital-to-Analog Converter (DAC) ● ●Fixed Voltage Reference (FVR) ● ●Numerically Controlled Oscillator (NCO) ● ●Temperature Indicator ● ●ComparatorsC1 ● ●Configurable Logic Cell (CLC)CLC1 ● ●CLC2 ● ●PWM ModulesPWM1 ● ●PWM2 ● ●PWM3 ● ●PWM4 ● ●TimersTimer0 ● ●Timer1 ● ●Timer2 ● ● 2011 Microchip Technology Inc. Preliminary DS41615A-page 9

PIC12(L)F1501FIGURE 1-1:PIC12(L)F1501 BLOCK DIAGRAMProgramFlash MemoryRAMCLKOUTTimingGenerationPORTACLKININTRCOscillatorCPU(Figure 2-1)MCLRC1CLC1CLC2Timer0Timer1Timer2CWG1NCO1Temp.IndicatorADC10-BitFVRPWM1 PWM2 PWM3PWM4DACNote 1: See applicable chapters for more information on peripherals.2: See Table 1-1 for peripherals available on specific devices.DS41615A-page 10 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501TABLE 1-2:NamePIC12(L)F1501 PINOUT DESCRIPTIONFunctionInputTypeOutputTypeDescriptionRA0/AN0/C1IN+/DACOUT1/CWG1B (1) /CLC2IN1/PWM2/ICSPDATRA0 TTL CMOS General purpose I/O.AN0 AN — A/D Channel input.C1IN+ AN — Comparator positive input.DACOUT1 — AN Digital-to-Analog Converter output.CWG1B — CMOS CWG complementary output.CLC2IN1 ST — Configurable Logic Cell source input.PWM2 — CMOS Pulse Width Module source output.ICSPDAT ST CMOS ICSP Data I/O.RA1/AN1/VREF+/C1IN0-/RA1 TTL CMOS General purpose I/O.NCO1 (1) /CLC2IN0/ICSPCLK AN1 AN — A/D Channel input.VREF+ AN — A/D Positive Voltage Reference input.C1IN0- AN — Comparator negative input.NCO1 — CMOS Numerically Controlled Oscillator output.CLC2IN0 ST — Configurable Logic Cell source input.ICSPCLK ST — ICSP Programming Clock.RA2/AN2/C1OUT/DACOUT2/ RA2 ST CMOS General purpose I/O.T0CKI/INT/PWM1/CLC1 (1) /CWG1A (1) AN2 AN — A/D Channel input./CWG1FLTC1OUT — CMOS Comparator output.DACOUT2 — AN Digital-to-Analog Converter output.T0CKI ST — Timer0 clock input.INT ST — External interrupt.PWM1 — CMOS Pulse Width Module source output.CLC1 — CMOS Configurable Logic Cell source output.CWG1A — CMOS CWG complementary output.CWG1FLT ST — Complementary Waveform Generator Fault input.RA3/CLC1IN0/VPP/T1G (2) /MCLR RA3 TTL — General purpose input.CLC1IN0 ST — Configurable Logic Cell source input.VPP HV — Programming voltage.T1G ST — Timer1 Gate input.MCLR ST — Master Clear with internal pull-up.RA4/AN3/C1IN1-/CWG1B (2) / RA4 TTL CMOS General purpose I/O.CLC1 (2) /PWM3/CLKOUT/T1G (1) AN3 AN — A/D Channel input.C1IN1- AN — Comparator negative input.CWG1B — CMOS CWG complementary output.CLC1 — CMOS Configurable Logic Cell source output.PWM3 — CMOS Pulse Width Module source output.CLKOUT — CMOS FOSC/4 output.T1G ST — Timer1 Gate input.Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open DrainTTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I 2 C = Schmitt Trigger input with I 2 CHV = High Voltage XTAL = Crystal levelsNote 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.2: Alternate location for peripheral pin function selected by the APFCON register. 2011 Microchip Technology Inc. Preliminary DS41615A-page 11

PIC12(L)F1501TABLE 1-2:NamePIC12(L)F1501 PINOUT DESCRIPTION (CONTINUED)FunctionInputTypeOutputTypeDescriptionRA5/CLKIN/T1CKI/CWG1A (2) / RA5 TTL CMOS General purpose I/O.NCO1 (2) /NCO1CLK/CLC1IN1/ CLKIN CMOS — External clock input (EC mode).CLC2/PWM4T1CKI ST — Timer1 clock input.CWG1A — CMOS CWG complementary output.NCO1 ST — Numerically Controlled Oscillator output.NCO1CLK ST — Numerically Controlled Oscillator Clock source input.CLC1IN1 ST — Configurable Logic Cell source input.CLC2 — CMOS Configurable Logic Cell source output.PWM4 — CMOS Pulse Width Module source output.VDD VDD Power — Positive supply.VSS VSS Power — Ground reference.Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open DrainTTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I 2 C = Schmitt Trigger input with I 2 CHV = High Voltage XTAL = Crystal levelsNote 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.2: Alternate location for peripheral pin function selected by the APFCON register.DS41615A-page 12 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15012.0 ENHANCED MID-RANGE CPUThis family of devices contain an enhanced mid-range8-bit CPU core. The CPU has 49 instructions. Interruptcapability includes automatic context saving. Thehardware stack is 16 levels deep and has Overflow andUnderflow Reset capability. Direct, Indirect, andRelative addressing modes are available. Two FileSelect Registers (FSRs) provide the ability to readprogram and data memory.• Automatic Interrupt Context Saving• 16-level Stack with Overflow and Underflow• File Select Registers• Instruction Set2.1 Automatic Interrupt ContextSavingDuring interrupts, certain registers are automaticallysaved in shadow registers and restored when returningfrom the interrupt. This saves stack space and usercode. See Section 7.5 “Automatic Context Saving”,for more information.2.2 16-level Stack with Overflow andUnderflowThese devices have an external stack memory 15 bitswide and 16 words deep. A Stack Overflow or Underflowwill set the appropriate bit (STKOVF or STKUNF)in the PCON register and, if enabled, will cause a softwareReset. See section Section 3.4 “Stack” for moredetails.2.3 File Select RegistersThere are two 16-bit File Select Registers (FSR). FSRscan access all file registers and program memory,which allows one Data Pointer for all memory. When anFSR points to program memory, there is one additionalinstruction cycle in instructions using INDF to allow thedata to be fetched. General purpose memory can nowalso be addressed linearly, providing the ability toaccess contiguous data larger than 80 bytes. There arealso new instructions to support the FSRs. SeeSection 3.5 “Indirect Addressing” for more details.2.4 Instruction SetThere are 49 instructions for the enhanced mid-rangeCPU to support the features of the CPU. SeeSection 26.0 “Instruction Set Summary” for moredetails. 2011 Microchip Technology Inc. Preliminary DS41615A-page 13

PIC12(L)F1501FIGURE 2-1:CORE BLOCK DIAGRAM15MUXConfiguration 15 Data BusProgram CounterFlashProgramMemory16-Level 8 StackRAM(13-bit) (15-bit)8Program14BusInstruction Regreg1515Direct Addr 78Program MemoryRead (PMR)5BSR FSR RegregFSR1 reg Reg12Addr MUXIndirectAddr12 12RAM AddrFSR0 regRegSTATUS Reg reg3MUXCLKINCLKOUTInstructionDecode and &ControlTimingGenerationPower-upTimerPower-onResetWatchdogTimerBrown-outReset8ALUW RegInternalOscillatorBlockVDDVSSDS41615A-page 14 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15013.0 MEMORY ORGANIZATIONThese devices contain the following types of memory:• Program Memory- Configuration Words- Device ID- User ID- Flash Program Memory• Data Memory- Core Registers- Special Function Registers- General Purpose RAM- Common RAMThe following features are associated with access andcontrol of program memory and data memory:• PCL and PCLATH• Stack• Indirect Addressing3.1 Program Memory OrganizationThe enhanced mid-range core has a 15-bit programcounter capable of addressing 32K x 14 programmemory space. Table 3-1 shows the memory sizesimplemented. Accessing a location above theseboundaries will cause a wrap-around within theimplemented memory space. The Reset vector is at0000h and the interrupt vector is at 0004h (seeFigure 3-1).TABLE 3-1:DeviceDEVICE SIZES AND ADDRESSESProgram Memory Size(Words)Last Program MemoryAddressHigh-Endurance FlashMemory Address Range (1)PIC12F15011,024 03FFh 0380h-03FFhPIC12LF1501Note 1: High-Endurance Flash applies to the low byte of each address in the range. 2011 Microchip Technology Inc. Preliminary DS41615A-page 15

PIC12(L)F1501FIGURE 3-1:CALL, CALLWRETURN, RETLWInterrupt, RETFIEPROGRAM MEMORY MAPAND STACK FORPIC12(L)F1501PC15Stack Level 0Stack Level 13.1.1 READING PROGRAM MEMORY ASDATAThere are two methods of accessing constants in programmemory. The first method is to use tables ofRETLW instructions. The second method is to set anFSR to point to the program memory.3.1.1.1 RETLW InstructionThe RETLW instruction can be used to provide accessto tables of constants. The recommended way to createsuch a table is shown in Example 3-1.On-chipProgramMemoryStack Level 15Reset VectorInterrupt VectorPage 0Rollover to Page 0Wraps to Page 0Wraps to Page 00000h0004h0005h03FFh0400hEXAMPLE 3-1:constantsBRWRETLW DATA0RETLW DATA1RETLW DATA2RETLW DATA3my_function;… LOTS OF CODE…MOVLW DATA_INDEXcall constants;… THE CONSTANT IS IN WRETLW INSTRUCTION;Add Index in W to;program counter to;select data;Index0 data;Index1 dataWraps to Page 0The BRW instruction makes this type of table very simpleto implement. If your code must remain portablewith previous generations of microcontrollers, then theBRW instruction is not available so the older table readmethod must be used.Rollover to Page 07FFFhDS41615A-page 16 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15013.1.1.2 Indirect Read with FSRThe program memory can be accessed as data by settingbit 7 of the FSRxH register and reading the matchingINDFx register. The MOVIW instruction will place thelower 8 bits of the addressed word in the W register.Writes to the program memory cannot be performed viathe INDF registers. Instructions that access the programmemory via the FSR require one extra instructioncycle to complete. Example 3-2 demonstrates accessingthe program memory via an FSR.The HIGH directive will set bit if a label points to alocation in program memory.EXAMPLE 3-2:ACCESSING PROGRAMMEMORY VIA FSRconstantsRETLW DATA0 ;Index0 dataRETLW DATA1 ;Index1 dataRETLW DATA2RETLW DATA3my_function;… LOTS OF CODE…MOVLW LOW constantsMOVWF FSR1LMOVLW HIGH constantsMOVWF FSR1HMOVIW 0[FSR1];THE PROGRAM MEMORY IS IN W3.2.1 CORE REGISTERSThe core registers contain the registers that directlyaffect the basic operation. The core registers occupythe first 12 addresses of every data memory bank(addresses x00h/x08h through x0Bh/x8Bh). Theseregisters are listed below in Table 3-2. For detailedinformation, see Table 3-4.TABLE 3-2:CORE REGISTERSAddressesx00h or x80hx01h or x81hx02h or x82hx03h or x83hx04h or x84hx05h or x85hx06h or x86hx07h or x87hx08h or x88hx09h or x89hx0Ah or x8Ahx0Bh or x8BhBANKxINDF0INDF1PCLSTATUSFSR0LFSR0HFSR1LFSR1HBSRWREGPCLATHINTCON3.2 Data Memory OrganizationThe data memory is partitioned into 32 memory bankswith 128 bytes in each bank. Each bank consists of(Figure 3-2):• 12 core registers• 20 Special Function Registers (SFR)• Up to 80 bytes of General Purpose RAM (GPR)• 16 bytes of common RAMThe active bank is selected by writing the bank numberinto the Bank Select Register (BSR). Unimplementedmemory will read as ‘0’. All data memory can beaccessed either directly (via instructions that use thefile registers) or indirectly via the two File SelectRegisters (FSR). See Section 3.5 “IndirectAddressing” for more information.Data memory uses a 12-bit address. The upper 7 bitsof the address define the Bank address and the lower5 bits select the registers/RAM in that bank. 2011 Microchip Technology Inc. Preliminary DS41615A-page 17

PIC12(L)F15013.2.1.1 STATUS RegisterThe STATUS register, shown in Register 3-1, contains:• the arithmetic status of the ALU• the Reset statusThe STATUS register can be the destination for anyinstruction, like any other register. If the STATUSregister is the destination for an instruction that affectsthe Z, DC or C bits, then the write to these three bits isdisabled. These bits are set or cleared according to thedevice logic. Furthermore, the TO and PD bits are notwritable. Therefore, the result of an instruction with theSTATUS register as destination may be different thanintended.REGISTER 3-1: STATUS: STATUS REGISTERFor example, CLRF STATUS will clear the upper threebits and set the Z bit. This leaves the STATUS registeras ‘000u u1uu’ (where u = unchanged).It is recommended, therefore, that only BCF, BSF,SWAPF and MOVWF instructions are used to alter theSTATUS register, because these instructions do notaffect any Status bits. For other instructions notaffecting any Status bits (Refer to Section 26.0“Instruction Set Summary”).Note 1:The C and DC bits operate as Borrowand Digit Borrow out bits, respectively, insubtraction.U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u— — — TO PD Z DC (1) C (1)bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on conditionbit 7-5 Unimplemented: Read as ‘0’bit 4TO: Time-Out bit1 = After power-up, CLRWDT instruction or SLEEP instruction0 = A WDT time-out occurredbit 3PD: Power-Down bit1 = After power-up or by the CLRWDT instruction0 = By execution of the SLEEP instructionbit 2Z: Zero bit1 = The result of an arithmetic or logic operation is zero0 = The result of an arithmetic or logic operation is not zerobit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) (1)1 = A carry-out from the 4th low-order bit of the result occurred0 = No carry-out from the 4th low-order bit of the resultbit 0 C: Carry/Borrow bit (1) (ADDWF, ADDLW, SUBLW, SUBWF instructions) (1)1 = A carry-out from the Most Significant bit of the result occurred0 = No carry-out from the Most Significant bit of the result occurredNote 1:For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of thesecond operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-orderbit of the source register.DS41615A-page 18 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15013.2.2 SPECIAL FUNCTION REGISTERThe Special Function Registers are registers used bythe application to control the desired operation ofperipheral functions in the device. The Special FunctionRegisters occupy the 20 bytes after the core registers ofevery data memory bank (addresses x0Ch/x8Chthrough x1Fh/x9Fh). The registers associated with theoperation of the peripherals are described in the appropriateperipheral chapter of this data sheet.3.2.3 GENERAL PURPOSE RAMThere are up to 80 bytes of GPR in each data memorybank. The Special Function Registers occupy the 20bytes after the core registers of every data memorybank (addresses x0Ch/x8Ch through x1Fh/x9Fh).3.2.3.1 Linear Access to GPRThe general purpose RAM can be accessed in anon-banked method via the FSRs. This can simplifyaccess to large memory structures. See Section 3.5.2“Linear Data Memory” for more information.3.2.4 COMMON RAMThere are 16 bytes of common RAM accessible from allbanks.FIGURE 3-2:7-bit Bank Offset00h0Bh0Ch1Fh20hBANKED MEMORYPARTITIONINGMemory RegionCore Registers(12 bytes)Special Function Registers(20 bytes maximum)General Purpose RAM(80 bytes maximum)6Fh70h7FhCommon RAM(16 bytes)3.2.5 DEVICE MEMORY MAPSThe memory maps for PIC12(L)F1501 are as shown inTable 3-3. 2011 Microchip Technology Inc. Preliminary DS41615A-page 19

PIC12(L)F1501TABLE 3-3: PIC12(L)F1501 MEMORY MAPBANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7000hCore Registers(Table 3-2)080hCore Registers(Table 3-2)100hCore Registers(Table 3-2)180hCore Registers(Table 3-2)200hCore Registers(Table 3-2)280hCore Registers(Table 3-2)300hCore Registers(Table 3-2)380hCore Registers(Table 3-2)00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch — 30Ch — 38Ch —00Dh — 08Dh — 10Dh — 18Dh — 20Dh — 28Dh — 30Dh — 38Dh —00Eh — 08Eh — 10Eh — 18Eh — 20Eh — 28Eh — 30Eh — 38Eh —00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh — 38Fh —010h — 090h — 110h — 190h — 210h — 290h — 310h — 390h —011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h — 291h — 311h — 391h IOCAP012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h — 292h — 312h — 392h IOCAN013h PIR3 093h PIE3 113h — 193h PMDATL 213h — 293h — 313h — 393h IOCAF014h — 094h — 114h — 194h PMDATH 214h — 294h — 314h — 394h —015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h — 295h — 315h — 395h —016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h — 296h — 316h — 396h —017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h — 297h — 317h — 397h —018h T1CON 098h — 118h DACCON0 198h — 218h — 298h — 318h — 398h —019h T1GCON 099h OSCCON 119h DACCON1 199h — 219h — 299h — 319h — 399h —01Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah — 21Ah — 29Ah — 31Ah — 39Ah —01Bh PR2 09Bh ADRESL 11Bh — 19Bh — 21Bh — 29Bh — 31Bh — 39Bh —01Ch T2CON 09Ch ADRESH 11Ch — 19Ch — 21Ch — 29Ch — 31Ch — 39Ch —01Dh — 09Dh ADCON0 11Dh APFCON 19Dh — 21Dh — 29Dh — 31Dh — 39Dh —01Eh — 09Eh ADCON1 11Eh — 19Eh — 21Eh — 29Eh — 31Eh — 39Eh —01Fh — 09Fh ADCON2 11Fh — 19Fh — 21Fh — 29Fh — 31Fh — 39Fh —020h04Fh050hGeneral PurposeRegister48 BytesUnimplementedRead as ‘0’0A0hUnimplementedRead as ‘0’120hUnimplementedRead as ‘0’1A0hUnimplementedRead as ‘0’220hUnimplementedRead as ‘0’2A0hUnimplementedRead as ‘0’320hUnimplementedRead as ‘0’06Fh 0EFh16Fh 1EFh 26Fh 2EFh 36Fh 3EFh070h0F0h170h1F0h270h2F0h370h3F0hCommon RAMCommon RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh3A0hUnimplementedRead as ‘0’Common RAM(Accesses70h – 7Fh)Legend: = Unimplemented data memory locations, read as ‘0’DS41615A-page 20 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501TABLE 3-3: PIC12(L)F1501 MEMORY MAP (CONTINUED)400h40BhBANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15Core Registers(Table 3-2)480h48BhCore Registers(Table 3-2)500h50BhCore Registers(Table 3-2)580h58BhCore Registers(Table 3-2)600h60BhCore Registers(Table 3-2)680h68BhCore Registers(Table 3-2)700h70BhCore Registers(Table 3-2)40Ch — 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch —40Dh — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70Dh — 78Dh —40Eh — 48Eh — 50Eh — 58Eh — 60Eh — 68Eh — 70Eh — 78Eh —40Fh — 48Fh — 50Fh — 58Fh — 60Fh — 68Fh — 70Fh — 78Fh —410h — 490h — 510h — 590h — 610h — 690h — 710h — 790h —411h — 491h — 511h — 591h — 611h PWM1DCL 691h CWG1DBR 711h — 791h —412h — 492h — 512h — 592h — 612h PWM1DCH 692h CWG1DBF 712h — 792h —413h — 493h — 513h — 593h — 613h PWM1CON 693h CWG1CON0 713h — 793h —414h — 494h — 514h — 594h — 614h PWM2DCL 694h CWG1CON1 714h — 794h —415h — 495h — 515h — 595h — 615h PWM2DCH 695h CWG1CON2 715h — 795h —416h — 496h — 516h — 596h — 616h PWM2CON 696h — 716h — 796h —417h — 497h — 517h — 597h — 617h PWM3DCL 697h — 717h — 797h —418h — 498h NCO1ACCL 518h — 598h — 618h PWM3DCH 698h — 718h — 798h —419h — 499h NCO1ACCH 519h — 599h — 619h PWM3CON 699h — 719h — 799h —41Ah — 49Ah NCO1ACCU 51Ah — 59Ah — 61Ah PWM4DCL 69Ah — 71Ah — 79Ah —41Bh — 49Bh NCO1INCL 51Bh — 59Bh — 61Bh PWM4DCH 69Bh — 71Bh — 79Bh —41Ch — 49Ch NCO1INCH 51Ch — 59Ch — 61Ch PWM4CON 69Ch — 71Ch — 79Ch —41Dh — 49Dh — 51Dh — 59Dh — 61Dh — 69Dh — 71Dh — 79Dh —41Eh — 49Eh NCO1CON 51Eh — 59Eh — 61Eh — 69Eh — 71Eh — 79Eh —41Fh — 49Fh NCO1CLK 51Fh — 59Fh — 61Fh — 69Fh — 71Fh — 79Fh —420h4A0h520h5A0h620h6A0h720h7A0h780h78BhCore Registers(Table 3-2)UnimplementedRead as ‘0’UnimplementedRead as ‘0’UnimplementedRead as ‘0’UnimplementedRead as ‘0’UnimplementedRead as ‘0’UnimplementedRead as ‘0’UnimplementedRead as ‘0’UnimplementedRead as ‘0’46Fh 4EFh 56Fh 5EFh 64Fh 6EFh 76Fh 7EFh470h4F0h570h5F0h650h6F0h770h7F0hCommon RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFhCommon RAM(Accesses70h – 7Fh)800h80Bh80ChBANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23Core Registers(Table 3-2 )UnimplementedRead as ‘0’880h88Bh88ChCore Registers(Table 3-2)UnimplementedRead as ‘0’900h90Bh90ChCore Registers(Table 3-2)UnimplementedRead as ‘0’980h98Bh98ChCore Registers(Table 3-2)UnimplementedRead as ‘0’A00hA0BhA0ChCore Registers(Table 3-2)UnimplementedRead as ‘0’A80hA8BhA8ChCore Registers(Table 3-2)UnimplementedRead as ‘0’B00hB0BhB0ChCore Registers(Table 3-2)UnimplementedRead as ‘0’86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh870h8F0h970h9F0hA70hAF0hB70hBF0hCommon RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFhLegend: = Unimplemented data memory locations, read as ‘0’B80hB8BhB8ChCore Registers(Table 3-2)UnimplementedRead as ‘0’Common RAM(Accesses70h – 7Fh) 2011 Microchip Technology Inc. Preliminary DS41615A-page 21

PIC12(L)F1501TABLE 3-3: PIC12(L)F1501 MEMORY MAP (CONTINUED)C00hBANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31Core Registers(Table 3-2)C80hCore Registers(Table 3-2)D00hCore Registers(Table 3-2)D80hCore Registers(Table 3-2)C0BhC8BhD0BhD8BhE0BhE8BhF0BhC0Ch — C8Ch — D0Ch — D8Ch — E0Ch — E8Ch — F0ChE00hCore Registers(Table 3-2)E80hCore Registers(Table 3-2)F00hCore Registers(Table 3-2)C0Dh — C8Dh — D0Dh — D8Dh — E0Dh — E8Dh — F0Dh F8DhC0Eh — C8Eh — D0Eh — D8Eh — E0Eh — E8Eh — F0Eh F8EhC0Fh — C8Fh — D0Fh — D8Fh — E0Fh — E8Fh — F0Fh F8FhC10h — C90h — D10h — D90h — E10h — E90h — F10h F90hC11h — C91h — D11h — D91h — E11h — E91h — F11h F91hC12h — C92h — D12h — D92h — E12h — E92h — F12h F92hC13h — C93h — D13h — D93h — E13h — E93h — F13h F93hC14h — C94h — D14h — D94h — E14h — E94h — F14h F94hC15h — C95h — D15h — D95h — E15h — E95h — F15h F95hC16h — C96h — D16h — D96h — E16h — E96h — F16h F96hC17h — C97h — D17h — D97h — E17h — E97h — F17h F97hC18h C19h — — C98h C99h — — D18h D19h — — D98h D99h — — E18h E19h — — E98h E99h — — F18hF19h See Table 3-3 forregister mappingdetails F98hF99hC1Ah — C9Ah — D1Ah — D9Ah — E1Ah — E9Ah — F1Ah F9AhC1Bh — C9Bh — D1Bh — D9Bh — E1Bh — E9Bh — F1Bh F9BhC1Ch — C9Ch — D1Ch — D9Ch — E1Ch — E9Ch — F1Ch F9ChC1Dh — C9Dh — D1Dh — D9Dh — E1Dh — E9Dh — F1Dh F9DhC1Eh — C9Eh — D1Eh — D9Eh — E1Eh — E9Eh — F1Eh F9EhC1Fh — C9Fh — D1Fh — D9Fh — E1Fh — E9Fh — F1Fh F9FhC20hCA0hD20hDA0hE20hEA0hF80hF8BhF8ChF20h FA0hCore Registers(Table 3-2)See Table 3-3 forregister mappingdetailsUnimplementedRead as ‘0’UnimplementedRead as ‘0’UnimplementedRead as ‘0’UnimplementedRead as ‘0’UnimplementedRead as ‘0’UnimplementedRead as ‘0’C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFhC70hCF0hD70hDF0hE70hEF0hF70hFF0hCommon RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)Common RAM(Accesses70h – 7Fh)CFFh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFhCommon RAM(Accesses70h – 7Fh)Legend: = Unimplemented data memory locations, read as ‘0’.DS41615A-page 22 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501TABLE 3-3:PIC12(L)F1501 MEMORY MAP (CONTINUED)Bank 30F0Ch —F0Dh —F0Eh —F0Fh CLCDATAF10h CLC1CONF11h CLC1POLF12h CLC1SEL0F13h CLC1SEL1F14h CLC1GLS0F15h CLC1GLS1F16h CLC1GLS2F17h CLC1GLS3F18h CLC2CONF19h CLC2POLF1Ah CLC2SEL0F1Bh CLC2SEL1F1Ch CLC2GLS0F1Dh CLC2GLS1F1Eh CLC2GLS2F1Fh CLC2GLS3F20hF6FhUnimplementedRead as ‘0’F8ChBank 31UnimplementedRead as ‘0’FE3hFE4h STATUS_SHADFE5h WREG_SHADFE6h BSR_SHADFE7h PCLATH_SHADFE8h FSR0L_SHADFE9h FSR0H_SHADFEAh FSR1L_SHADFEBh FSR1H_SHADFECh —FEDh STKPTRFEEhTOSLFEFhTOSHLegend: = Unimplemented data memory locations, read as ‘0’. 2011 Microchip Technology Inc. Preliminary DS41615A-page 23

PIC12(L)F15013.2.6 CORE FUNCTION REGISTERSSUMMARYThe Core Function registers listed in Table 3-4 can beaddressed from any Bank.TABLE 3-4:CORE FUNCTION REGISTERS SUMMARYAddr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value onPOR, BORValue on allother ResetsBank 0-31x00h orAddressing this location uses contents of FSR0H/FSR0L to address data memoryINDF0x80h(not a physical register)xxxx xxxx uuuu uuuux01h orAddressing this location uses contents of FSR1H/FSR1L to address data memoryINDF1x81h(not a physical register)xxxx xxxx uuuu uuuux02h orPCLx82hProgram Counter (PC) Least Significant Byte 0000 0000 0000 0000x03h orSTATUSx83h— — — TO PD Z DC C ---1 1000 ---q quuux04h orFSR0Lx84hIndirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuux05h orFSR0Hx85hIndirect Data Memory Address 0 High Pointer 0000 0000 0000 0000x06h orFSR1Lx86hIndirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuux07h orFSR1Hx87hIndirect Data Memory Address 1 High Pointer 0000 0000 0000 0000x08h orBSRx88h— — — BSR ---0 0000 ---0 0000x09h orWREGx89hWorking Register 0000 0000 uuuu uuuux0Ah orx8AhPCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000x0Bh orx8BhINTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.Shaded locations are unimplemented, read as ‘0’.DS41615A-page 24 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501TABLE 3-5:SPECIAL FUNCTION REGISTER SUMMARYAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value onPOR, BORValue on allotherResetsBank 000Ch PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx00Dh — Unimplemented — —00Eh — Unimplemented — —00Fh — Unimplemented — —010h — Unimplemented — —011h PIR1 TMR1GIF ADIF — — — — TMR2IF TMR1IF 00-- --00 00-- --00012h PIR2 — — C1IF — — NCO1IF — — --0- -0-- --0- -0--013h PIR3 — — — — — — CLC2IF CLC1IF ---- --00 ---- --00014h — Unimplemented — —015h TMR0 Holding Register for the 8-bit Timer0 Count xxxx xxxx uuuu uuuu016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu uuuu017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu uuuu018h T1CON TMR1CS T1CKPS — T1SYNC — TMR1ON 0000 -0-0 uuuu -u-u019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS 0000 0x00 uuuu uxuuDONE01Ah TMR2 Timer2 Module Register 0000 0000 0000 000001Bh PR2 Timer2 Period Register 1111 1111 1111 111101Ch T2CON — T2OUTPS TMR2ON T2CKPS -000 0000 -000 000001Dh — Unimplemented — —01Eh — Unimplemented — —01Fh — Unimplemented — —Bank 108Ch TRISA — — TRISA5 TRISA4 — (2) TRISA2 TRISA1 TRISA0 --11 1111 --11 111108Dh — Unimplemented — —08Eh — Unimplemented — —08Fh — Unimplemented — —090h — Unimplemented — —091h PIE1 TMR1GIE ADIE — — — — TMR2IE TMR1IE 00-- --00 00-- --00092h PIE2 — — C1IE — — NCO1IE — — --0- -0-- -00- -0--093h PIE3 — — — — — — CLC2IE CLC1IE ---- --00 ---- --00094h — Unimplemented — —095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS 1111 1111 1111 1111096h PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 00-1 11qq qq-q qquu097h WDTCON — — WDTPS SWDTEN --01 0110 --01 0110098h — Unimplemented — —099h OSCCON — IRCF — SCS -011 1-00 -011 1-0009Ah OSCSTAT — — — HFIOFR — — LFIOFR HFIOFS ---0 --00 ---q --qq09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu09Dh ADCON0 — CHS GO/DONE ADON -000 0000 -000 000009Eh ADCON1 ADFM ADCS — — ADPREF 0000 --00 0000 --0009Fh ADCON2 TRIGSEL — — — — 0000 ---- 0000 ----Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.Note 1: PIC12F1501 only.2: Unimplemented, read as ‘1’. 2011 Microchip Technology Inc. Preliminary DS41615A-page 25

PIC12(L)F1501TABLE 3-5:Bank 2SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value onPOR, BORValue on allotherResets10Ch LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 --xx -xxx --uu -uuu10Dh — Unimplemented — —10Eh — Unimplemented — —10Fh — Unimplemented — —110h — Unimplemented — —111h CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 0000 -100 0000 -100112h CM1CON1 C1INTP C1INTN C1PCH — C1NCH 0000 -000 0000 -000113h — Unimplemented — —114h — Unimplemented — —115h CMOUT — — — — — — — MC1OUT ---- ---0 ---- ---0116h BORCON SBOREN BORFS — — — — — BORRDY 10-- ---q uu-- ---u117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR ADFVR 0q00 0000 0q00 0000118h DACCON0 DACEN — DACOE1 DACOE2 — DACPSS — — 0-00 -0-- 0-00 -0--119h DACCON1 — — DACR ---0 0000 ---0 000011Ahto — Unimplemented — —11Ch11Dh APFCON CWG1BSEL CWG1ASEL — — T1GSEL — CLC1SEL NCO1SEL 00-- 0-00 00-- 0-0011Eh — Unimplemented — —11Fh — Unimplemented — —Bank 318Ch ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -11118Dh — Unimplemented — —18Eh — Unimplemented — —18Fh — Unimplemented — —190h — Unimplemented — —191h PMADRL Flash Program Memory Address Register Low Byte 0000 0000 0000 0000192h PMADRH — Flash Program Memory Address Register High Byte -000 0000 -000 0000193h PMDATL Flash Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu194h PMDATH — — Flash Program Memory Read Data Register High Byte --xx xxxx --uu uuuu195h PMCON1 — (2) CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000196h PMCON2 Flash Program Memory Control Register 2 0000 0000 0000 0000197h VREGCON (1) — — — — — — VREGPM Reserved ---- --01 ---- --01198hto19Fh— Unimplemented — —Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.Note 1: PIC12F1501 only.2: Unimplemented, read as ‘1’.DS41615A-page 26 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501TABLE 3-5:Bank 4SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value onPOR, BORValue on allotherResets20Ch WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 111120Dhto — Unimplemented — —21FhBank 528Chto — Unimplemented — —29FhBank 630Chto — Unimplemented — —31FhBank 738Chto — Unimplemented — —390h391h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000392h IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000393h IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000394hto — Unimplemented — —39FhBank 840Chto — Unimplemented — —41FhBank 948Chto — Unimplemented — —497h498h NCO1ACCL NCO1ACC 0000 0000 0000 0000499h NCO1ACCH NCO1ACC 0000 0000 0000 000049Ah NCO1ACCU NCO1ACC 0000 0000 0000 000049Bh NCO1INCL NCO1INC 0000 0000 0000 000049Ch NCO1INCH NCO1INC 0000 0000 0000 000049Dh — Unimplemented — —49Eh NCO1CON N1EN N1OE N1OUT N1POL — — — N1PFM 0000 ---0 0000 ---049Fh NCO1CLK N1PWS — — — N1CKS 0000 --00 0000 --00Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.Note 1: PIC12F1501 only.2: Unimplemented, read as ‘1’. 2011 Microchip Technology Inc. Preliminary DS41615A-page 27

PIC12(L)F1501TABLE 3-5:Bank 10SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value onPOR, BORValue on allotherResets50Chto — Unimplemented — —51FhBank 1158Chto — Unimplemented — —59FhBank 1260Chto — Unimplemented — —610h611h PWM1DCL PWM1DCL — — — — — — 00-- ---- 00-- ----612h PWM1DCH PWM1DCH xxxx xxxx uuuu uuuu613h PWM1CON0 PWM1EN PWM1OE PWM1OUT PWM1POL — — — — 0000 ---- 0000 ----614h PWM2DCL PWM2DCL — — — — — — 00-- ---- 00-- ----615h PWM2DCH PWM2DCH xxxx xxxx uuuu uuuu616h PWM2CON0 PWM2EN PWM2OE PWM2OUT PWM2POL — — — — 0000 ---- 0000 ----617h PWM3DCL PWM3DCL — — — — — — 00-- ---- 00-- ----618h PWM3DCH PWM3DCH xxxx xxxx uuuu uuuu619h PWM3CON0 PWM3EN PWM3OE PWM3OUT PWM3POL — — — — 0000 ---- 0000 ----61Ah PWM4DCL PWM4DCL — — — — — — 00-- ---- 00-- ----61Bh PWM4DCH PWM4DCH xxxx xxxx uuuu uuuu61Ch PWM4CON0 PWM4EN PWM4OE PWM4OUT PWM4POL — — — — 0000 ---- 0000 ----61Dhto — Unimplemented — —61FhBank 1368Chto — Unimplemented — —690h691h CWG1DBR — — CWG1DBR --00 0000 --00 0000692h CWG1DBF — — CWG1DBF --xx xxxx --xx xxxx693h CWG1CON0 G1EN G1OEB G1OEA G1POLB G1POLA — — G1CS0 0000 0--0 0000 0--0694h CWG1CON1 G1ASDLB G1ASDLA — G1IS 0000 -000 0000 -000695h CWG1CON2 G1ASE G1ARSEN — — — G1ASDC1 G1ASDFLT G1ASDCLC2 00-- -000 00-- -000696hto — Unimplemented — —69FhBank 14-29Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.Note 1: PIC12F1501 only.2: Unimplemented, read as ‘1’.DS41615A-page 28 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501TABLE 3-5:SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value onPOR, BORValue on allotherResetsBanks 14-29x0Ch/ — Unimplemented — —x8Ch—x1Fh/x9FhBank 30F0Chto — Unimplemented — —F0EhF0Fh CLCDATA — — — — — — MLC1OUT MLC2OUT ---- --00 ---- --00F10h CLC1CON LC1EN LC1OE LC1OUT LC1INTP LC1INTN LC1MODE 0000 0000 0000 0000F11h CLC1POL LC1POL — — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL 0--- xxxx 0--- uuuuF12h CLC1SEL0 — LC1D2S — LC1D1S -xxx -xxx -uuu -uuuF13h CLC1SEL1 — LC1D4S — LC1D3S -xxx -xxx -uuu -uuuF14h CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx uuuu uuuuF15h CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N xxxx xxxx uuuu uuuuF16h CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N xxxx xxxx uuuu uuuuF17h CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N xxxx xxxx uuuu uuuuF18h CLC2CON LC2EN LC2OE LC2OUT LC2INTP LC2INTN LC2MODE 0000 0000 0000 0000F19h CLC2POL LC2POL — — — LC2G4POL LC2G3POL LC2G2POL LC2G1POL 0--- xxxx 0--- uuuuF1Ah CLC2SEL0 — LC2D2S — LC2D1S -xxx -xxx -uuu -uuuF1Bh CLC2SEL1 — LC2D4S — LC2D3S -xxx -xxx -uuu -uuuF1Ch CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N xxxx xxxx uuuu uuuuF1Dh CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N xxxx xxxx uuuu uuuuF1Eh CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N xxxx xxxx uuuu uuuuF1Fh CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N xxxx xxxx uuuu uuuuF20htoF6Fh— Unimplemented — —Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.Note 1: PIC12F1501 only.2: Unimplemented, read as ‘1’. 2011 Microchip Technology Inc. Preliminary DS41615A-page 29

PIC12(L)F1501TABLE 3-5:Bank 31F8Ch — Unimplemented — ——FE3hFE4h STATUS_SHAD— — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuuFE5hFE6hFE7hFE8hFE9hFEAhFEBhWREG_SHADBSR_SHADPCLATH_SHADFSR0L_SHADFSR0H_SHADFSR1L_SHADFSR1H_SHADSPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Working Register Shadowxxxx xxxx uuuu uuuu— — — Bank Select Register Shadow ---x xxxx ---u uuuu— Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuuIndirect Data Memory Address 0 Low Pointer ShadowIndirect Data Memory Address 0 High Pointer ShadowIndirect Data Memory Address 1 Low Pointer ShadowIndirect Data Memory Address 1 High Pointer ShadowValue onPOR, BORValue on allotherResetsxxxx xxxx uuuu uuuuxxxx xxxx uuuu uuuuxxxx xxxx uuuu uuuuxxxx xxxx uuuu uuuuFECh — Unimplemented — —FEDh STKPTR — — — Current Stack Pointer ---1 1111 ---1 1111FEEh TOSL Top-of-Stack Low byte xxxx xxxx uuuu uuuuFEFh TOSH — Top-of-Stack High byte -xxx xxxx -uuu uuuuLegend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’.Note 1: PIC12F1501 only.2: Unimplemented, read as ‘1’.DS41615A-page 30 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15013.3 PCL and PCLATHThe Program Counter (PC) is 15 bits wide. The low bytecomes from the PCL register, which is a readable andwritable register. The high byte (PC) is not directlyreadable or writable and comes from PCLATH. On anyReset, the PC is cleared. Figure 3-3 shows the fivesituations for the loading of the PC.FIGURE 3-3:PCLATHPCLATH14PC614PC14PC6 4LOADING OF PC INDIFFERENT SITUATIONSPCH PCL 070PCH PCL 00ALU Result118OPCODE PCH PCL 0Instruction withPCL asDestinationGOTO, CALLCALLW3.3.2 COMPUTED GOTOA computed GOTO is accomplished by adding an offset tothe program counter (ADDWF PCL). When performing atable read using a computed GOTO method, care shouldbe exercised if the table location crosses a PCL memoryboundary (each 256-byte block). Refer to ApplicationNote AN556, “Implementing a Table Read” (DS00556).3.3.3 COMPUTED FUNCTION CALLSA computed function CALL allows programs to maintaintables of functions and provide another way to executestate machines or look-up tables. When performing atable read using a computed function CALL, careshould be exercised if the table location crosses a PCLmemory boundary (each 256-byte block).If using the CALL instruction, the PCH and PCLregisters are loaded with the operand of the CALLinstruction. PCH is loaded with PCLATH.The CALLW instruction enables computed calls by combiningPCLATH and W to form the destination address.A computed CALLW is accomplished by loading the Wregister with the desired address and executing CALLW.The PCL register is loaded with the value of W andPCH is loaded with PCLATH.PCLATH614PC708WPCH PCL 015PC + WBRW3.3.4 BRANCHINGThe branching instructions add an offset to the PC.This allows relocatable code and code that crossespage boundaries. There are two forms of branching,BRW and BRA. The PC will have incremented to fetchthe next instruction in both cases. When using eitherbranching instruction, a PCL memory boundary may becrossed.14PCPCH PCL 015BRAIf using BRW, load the W register with the desiredunsigned address and execute BRW. The entire PC willbe loaded with the address PC + 1 + W.PC + OPCODE If using BRA, the entire PC will be loaded with PC + 1 +,the signed value of the operand of the BRA instruction.3.3.1 MODIFYING PCLExecuting any instruction with the PCL register as thedestination simultaneously causes the Program CounterPC bits (PCH) to be replaced by the contentsof the PCLATH register. This allows the entire contentsof the program counter to be changed by writing thedesired upper 7 bits to the PCLATH register. When thelower 8 bits are written to the PCL register, all 15 bits ofthe program counter will change to the values containedin the PCLATH register and those being writtento the PCL register. 2011 Microchip Technology Inc. Preliminary DS41615A-page 31

PIC12(L)F15013.4 StackAll devices have a 16-level x 15-bit wide hardwarestack (refer to Figures 3-4 through 3-7). The stackspace is not part of either program or data space. ThePC is PUSHed onto the stack when CALL or CALLWinstructions are executed or an interrupt causes abranch. The stack is POPed in the event of a RETURN,RETLW or a RETFIE instruction execution. PCLATH isnot affected by a PUSH or POP operation.The stack operates as a circular buffer if the STVRENbit is programmed to ‘0‘ (Configuration Words). Thismeans that after the stack has been PUSHed sixteentimes, the seventeenth PUSH overwrites the value thatwas stored from the first PUSH. The eighteenth PUSHoverwrites the second PUSH (and so on). TheSTKOVF and STKUNF flag bits will be set on an Overflow/Underflow,regardless of whether the Reset isenabled.Note 1:There are no instructions/mnemonicscalled PUSH or POP. These are actionsthat occur from the execution of theCALL, CALLW, RETURN, RETLW andRETFIE instructions or the vectoring toan interrupt address.3.4.1 ACCESSING THE STACKThe stack is available through the TOSH, TOSL andSTKPTR registers. STKPTR is the current value of theStack Pointer. TOSH:TOSL register pair points to theTOP of the stack. Both registers are read/writable. TOSis split into TOSH and TOSL due to the 15-bit size of thePC. To access the stack, adjust the value of STKPTR,which will position TOSH:TOSL, then read/write toTOSH:TOSL. STKPTR is 5 bits to allow detection ofoverflow and underflow.Note:Care should be taken when modifying theSTKPTR while interrupts are enabled.During normal program operation, CALL, CALLW andInterrupts will increment STKPTR while RETLW,RETURN, and RETFIE will decrement STKPTR. At anytime, STKPTR can be inspected to see how muchstack is left. The STKPTR always points at the currentlyused place on the stack. Therefore, a CALL or CALLWwill increment the STKPTR and then write the PC, anda return will unload the PC and then decrement theSTKPTR.Reference Figure 3-4 through Figure 3-7 for examplesof accessing the stack.FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1TOSH:TOSL0x0F0x0ESTKPTR = 0x1FStack Reset Disabled(STVREN = 0)0x0D0x0C0x0B0x0A0x090x080x070x060x050x04Initial Stack Configuration:After Reset, the stack is empty. Theempty stack is initialized so the StackPointer is pointing at 0x1F. If the StackOverflow/Underflow Reset is enabled, theTOSH/TOSL registers will return ‘0’. Ifthe Stack Overflow/Underflow Reset isdisabled, the TOSH/TOSL registers willreturn the contents of stack address 0x0F.0x030x020x01TOSH:TOSL0x000x1F0x0000STKPTR = 0x1FStack Reset Enabled(STVREN = 1)DS41615A-page 32 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501FIGURE 3-5: ACCESSING THE STACK EXAMPLE 20x0F0x0E0x0D0x0C0x0B0x0A0x090x080x070x06This figure shows the stack configurationafter the first CALL or a single interrupt.If a RETURN instruction is executed, thereturn address will be placed in theProgram Counter and the Stack Pointerdecremented to the empty state (0x1F).0x050x040x030x020x01TOSH:TOSL0x00Return AddressSTKPTR = 0x00FIGURE 3-6: ACCESSING THE STACK EXAMPLE 30x0F0x0E0x0D0x0C0x0B0x0A0x09After seven CALLs or six CALLs and aninterrupt, the stack looks like the figureon the left. A series of RETURN instructionswill repeatedly place the return addressesinto the Program Counter and pop the stack.0x080x07TOSH:TOSL0x06Return AddressSTKPTR = 0x060x05Return Address0x04Return Address0x03Return Address0x02Return Address0x01Return Address0x00Return Address 2011 Microchip Technology Inc. Preliminary DS41615A-page 33

PIC12(L)F1501FIGURE 3-7: ACCESSING THE STACK EXAMPLE 40x0FReturn Address0x0EReturn Address0x0DReturn Address0x0CReturn Address0x0BReturn Address0x0A0x090x080x070x060x05Return AddressReturn AddressReturn AddressReturn AddressReturn AddressReturn AddressWhen the stack is full, the next CALL oran interrupt will set the Stack Pointer to0x10. This is identical to address 0x00so the stack will wrap and overwrite thereturn address at 0x00. If the StackOverflow/Underflow Reset is enabled, aReset will occur and location 0x00 willnot be overwritten.0x04Return Address0x03Return Address0x02Return Address0x01Return AddressTOSH:TOSL0x00Return AddressSTKPTR = 0x103.4.2 OVERFLOW/UNDERFLOW RESETIf the STVREN bit in Configuration Words isprogrammed to ‘1’, the device will be reset if the stackis PUSHed beyond the sixteenth level or POPedbeyond the first level, setting the appropriate bits(STKOVF or STKUNF, respectively) in the PCONregister.3.5 Indirect AddressingThe INDFn registers are not physical registers. Anyinstruction that accesses an INDFn register actuallyaccesses the register at the address specified by theFile Select Registers (FSR). If the FSRn addressspecifies one of the two INDFn registers, the read willreturn ‘0’ and the write will not occur (though Status bitsmay be affected). The FSRn register value is createdby the pair FSRnH and FSRnL.The FSR registers form a 16-bit address that allows anaddressing space with 65536 locations. These locationsare divided into three memory regions:• Traditional Data Memory• Linear Data Memory• Program Flash MemoryDS41615A-page 34 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501FIGURE 3-8:INDIRECT ADDRESSING0x00000x0000TraditionalData Memory0x0FFF0x10000x1FFF0x20000x0FFFReservedLinearData MemoryFSRAddressRange0x29AF0x29B00x7FFF0x8000Reserved0x0000ProgramFlash Memory0xFFFF0x7FFFNote:Not all memory regions are completely implemented. Consult device memory tables for memory limits. 2011 Microchip Technology Inc. Preliminary DS41615A-page 35

PIC12(L)F15013.5.1 TRADITIONAL DATA MEMORYThe traditional data memory is a region from FSRaddress 0x000 to FSR address 0xFFF. The addressescorrespond to the absolute addresses of all SFR, GPRand common registers.FIGURE 3-9:TRADITIONAL DATA MEMORY MAPDirect AddressingIndirect Addressing4 BSR 0 6 From Opcode 07 FSRxH 00 0 0 07 FSRxL 0Bank SelectLocation SelectBank Select00000 00001 00010 111110x00Location Select0x7FBank 0 Bank 1 Bank 2 Bank 31DS41615A-page 36 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15013.5.2 LINEAR DATA MEMORYThe linear data memory is the region from FSRaddress 0x2000 to FSR address 0x29AF. This region isa virtual region that points back to the 80-byte blocks ofGPR memory in all the banks.Unimplemented memory reads as 0x00. Use of thelinear data memory region allows buffers to be largerthan 80 bytes because incrementing the FSR beyondone bank will go directly to the GPR memory of the nextbank.The 16 bytes of common memory are not included inthe linear data memory region.FIGURE 3-10:7 FSRnH0 0 1Location SelectLINEAR DATA MEMORYMAP0 7 FSRnL 00x20000x020Bank 00x06F0x0A0Bank 10x0EF0x120Bank 20x16F3.5.3 PROGRAM FLASH MEMORYTo make constant data access easier, the entireprogram Flash memory is mapped to the upper half ofthe FSR address space. When the MSB of FSRnH isset, the lower 15 bits are the address in programmemory which will be accessed through INDF. Only thelower 8 bits of each memory location is accessible viaINDF. Writing to the program Flash memory cannot beaccomplished via the FSR/INDF interface. Allinstructions that access program Flash memory via theFSR/INDF interface will require one additionalinstruction cycle to complete.FIGURE 3-11:71FSRnHLocation SelectPROGRAM FLASHMEMORY MAP0 7 FSRnL 00x80000x0000ProgramFlashMemory(low 8bits)0x29AF0xF20Bank 300xF6F0xFFFF0x7FFF 2011 Microchip Technology Inc. Preliminary DS41615A-page 37

PIC12(L)F1501NOTES:DS41615A-page 38 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15014.0 DEVICE CONFIGURATIONDevice Configuration consists of Configuration Words,Code Protection and Device ID.4.1 Configuration WordsThere are several Configuration Word bits that allowdifferent oscillator and memory protection options.These are implemented as Configuration Word 1 at8007h and Configuration Word 2 at 8008h. 2011 Microchip Technology Inc. Preliminary DS41615A-page 39

PIC12(L)F1501REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1U-1 U-1 R/P-1 R/P-1 R/P-1 U-1— — CLKOUTEN BOREN —bit 13 bit 8R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1CP MCLRE PWRTE WDTE — FOSCbit 7 bit 0Legend:R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erasebit 13-12 Unimplemented: Read as ‘1’bit 11 CLKOUTEN: Clock Out Enable bit1 = CLKOUT function is disabled. I/O function on the CLKOUT pin0 = CLKOUT function is enabled on the CLKOUT pinbit 10-9 BOREN: Brown-out Reset Enable bits (1)11 = BOR enabled10 = BOR enabled during operation and disabled in Sleep01 = BOR controlled by SBOREN bit of the BORCON register00 = BOR disabledbit 8 Unimplemented: Read as ‘1’bit 7 CP: Code Protection bit (2)1 = Program memory code protection is disabled0 = Program memory code protection is enabledbit 6 MCLRE: MCLR/VPP Pin Function Select bitIf LVP bit = 1:This bit is ignored.If LVP bit = 0:1 =MCLR/VPP pin function is MCLR; Weak pull-up enabled.0 =MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control ofWPUE3 bit.bit 5 PWRTE: Power-Up Timer Enable bit1 = PWRT disabled0 = PWRT enabledbit 4-3 WDTE: Watchdog Timer Enable bits11 = WDT enabled10 = WDT enabled while running and disabled in Sleep01 = WDT controlled by the SWDTEN bit in the WDTCON register00 = WDT disabledbit 2 Unimplemented: Read as ‘1’bit 1-0 FOSC: Oscillator Selection bits11 = ECH: External Clock, High-Power mode: on CLKIN pin10 = ECM: External Clock, Medium-Power mode: on CLKIN pin01 = ECL: External Clock, Low-Power mode: on CLKIN pin00 = INTOSC oscillator: I/O function on CLKIN pinNote 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.2: Once enabled, code-protect can only be disabled by bulk erasing the device.DS41615A-page 40 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2R/P-1 U-1 R/P-1 R/P-1 R/P-1 U-1LVP — LPBOR BORV STVREN —bit 13 bit 8U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1— — — — — — WRTbit 7 bit 0Legend:R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erasebit 13 LVP: Low-Voltage Programming Enable bit (1)1 = Low-voltage programming enabled0 = High-voltage on MCLR must be used for programmingbit 12 Unimplemented: Read as ‘1’bit 11 LPBOR: Low-Power BOR Enable bit1 = Low-Power Brown-out Reset is disabled0 = Low-Power Brown-out Reset is enabledbit 10 BORV: Brown-out Reset Voltage Selection bit (2)1 = Brown-out Reset voltage (Vbor), low trip point selected0 = Brown-out Reset voltage (Vbor), high trip point selectedbit 9 STVREN: Stack Overflow/Underflow Reset Enable bit1 = Stack Overflow or Underflow will cause a Reset0 = Stack Overflow or Underflow will not cause a Resetbit 8-2 Unimplemented: Read as ‘1’bit 1-0 WRT: Flash Memory Self-Write Protection bits1 kW Flash memory:11 = Write protection off10 = 000h to 0FFh write-protected, 100h to 3FFh may be modified01 = 000h to 1FFh write-protected, 200h to 3FFh may be modified00 = 000h to 3FFh write-protected, no addresses may be modifiedNote 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.2: See Vbor parameter for specific trip point voltages. 2011 Microchip Technology Inc. Preliminary DS41615A-page 41

PIC12(L)F15014.2 Code ProtectionCode protection allows the device to be protected fromunauthorized access. Internal access to the programmemory is unaffected by any code protection setting.4.2.1 PROGRAM MEMORY PROTECTIONThe entire program memory space is protected fromexternal reads and writes by the CP bit in ConfigurationWords. When CP = 0, external reads and writes ofprogram memory are inhibited and a read will return all‘0’s. The CPU can continue to read program memory,regardless of the protection bit settings. Writing theprogram memory is dependent upon the writeprotection setting. See Section 4.3 “WriteProtection” for more information.4.3 Write ProtectionWrite protection allows the device to be protected fromunintended self-writes. Applications, such asbootloader software, can be protected while allowingother regions of the program memory to be modified.The WRT bits in Configuration Words define thesize of the program memory block that is protected.4.4 User IDFour memory locations (8000h-8003h) are designated asID locations where the user can store checksum or othercode identification numbers. These locations arereadable and writable during normal execution. SeeSection 10.4 “User ID, Device ID and ConfigurationWord Access” for more information on accessing thesememory locations. For more information on checksumcalculation, see the “PIC12(L)F1501/PIC16(L)F150XMemory Programming Specification” (DS41573).DS41615A-page 42 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15014.5 Device ID and Revision IDThe memory location 8006h is where the Device ID andRevision ID are stored. The upper nine bits hold theDevice ID. The lower five bits hold the Revision ID. SeeSection 10.4 “User ID, Device ID and ConfigurationWord Access” for more information on accessingthese memory locations.Development tools, such as device programmers anddebuggers, may be used to read the Device ID andRevision ID.REGISTER 4-3:DEVICEID: DEVICE ID REGISTERR R R R R RDEVbit 13 bit 8R R R R R R R RDEVREVbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is cleared P = Programmable bitbit 13-5DEV: Device ID bitsDeviceDEVICEID ValuesDEVREVPIC12F1501 10 1100 110 x xxxxPIC12LF1501 10 1101 100 x xxxxbit 4-0REV: Revision ID bitsThese bits are used to identify the revision (see Table under DEV above). 2011 Microchip Technology Inc. Preliminary DS41615A-page 43

PIC12(L)F1501NOTES:DS41615A-page 44 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15015.0 OSCILLATOR MODULE5.1 OverviewThe oscillator module has a wide variety of clocksources and selection features that allow it to be usedin a wide range of applications while maximizing performanceand minimizing power consumption. Figure 5-1illustrates a block diagram of the oscillator module.The oscillator module can be configured in one of thefollowing clock modes.1. ECL – External Clock Low-Power mode(0 MHz to 0.5 MHz)2. ECM – External Clock Medium-Power mode(0.5 MHz to 4 MHz)3. ECH – External Clock High-Power mode(4 MHz to 20 MHz)4. INTOSC – Internal oscillator (31 kHz to 16 MHz)Clock Source modes are selected by the FOSCbits in the Configuration Words. The FOSC bitsdetermine the type of oscillator that will be used whenthe device is first powered.The EC clock mode relies on an external logic levelsignal as the device clock source.The INTOSC internal oscillator block produces low andhigh-frequency clock sources, designated LFINTOSCand HFINTOSC. (see Internal Oscillator Block,Figure 5-1). A wide selection of device clockfrequencies may be derived from these clock sources.FIGURE 5-1:SIMPLIFIED PIC ® MCU CLOCK SOURCE BLOCK DIAGRAMCLKINCLKIN ECECSleepMUXCPU andPeripheralsInternalOscillatorBlock16 MHzSource31 kHzSource16 MHz(HFINTOSC)Postscaler16 MHz8 MHz4 MHz2 MHz1 MHz500 kHz250 kHz125 kHz62.5 kHz31.25 kHz31 kHzIRCFMUXInternal OscillatorFOSCClockControlSCS31 kHz (LFINTOSC)WDT, PWRT and other modules 2011 Microchip Technology Inc. Preliminary DS41615A-page 45

PIC12(L)F15015.2 Clock Source TypesClock sources can be classified as external or internal.External clock sources rely on external circuitry for theclock source to function. Examples are: oscillator modules(EC mode).Internal clock sources are contained within theoscillator module. The oscillator block has two internaloscillators that are used to generate two system clocksources: the 16 MHz High-Frequency InternalOscillator (HFINTOSC) and the 31 kHz Low-FrequencyInternal Oscillator (LFINTOSC).The system clock can be selected between external orinternal clock sources via the System Clock Select(SCS) bits in the OSCCON register. See Section 5.3“Clock Switching” for additional information.5.2.1 EXTERNAL CLOCK SOURCESAn external clock source can be used as the devicesystem clock by performing one of the followingactions:• Program the FOSC bits in the ConfigurationWords to select an external clock source that willbe used as the default system clock upon adevice Reset.• Clear the SCS bits in the OSCCON registerto switch the system clock source to:- An external clock source determined by thevalue of the FOSC bits.See Section 5.3 “Clock Switching”for more information.5.2.1.1 EC ModeThe External Clock (EC) mode allows an externallygenerated logic level signal to be the system clocksource. When operating in this mode, an external clocksource is connected to the CLKIN input. CLKOUT isavailable for general purpose I/O or CLKOUT.Figure 5-2 shows the pin connections for EC mode.EC mode has 3 power modes to select from throughConfiguration Words:• High power, 4-20 MHz (FOSC = 11)• Medium power, 0.5-4 MHz (FOSC = 10)• Low power, 0-0.5 MHz (FOSC = 01)When EC mode is selected, there is no delay in operationafter a Power-on Reset (POR) or wake-up fromSleep. Because the PIC ® MCU design is fully static,stopping the external clock input will have the effect ofhalting the device while leaving all data intact. Uponrestarting the external clock, the device will resumeoperation as if no time had elapsed.FIGURE 5-2:Clock fromExt. SystemFOSC/4 or I/O (1)EXTERNAL CLOCK (EC)MODE OPERATIONCLKINCLKOUTPIC ® MCUNote 1: Output depends upon CLKOUTEN bit of theConfiguration Words.DS41615A-page 46 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15015.2.2 INTERNAL CLOCK SOURCESThe device may be configured to use the internal oscillatorblock as the system clock by performing one of thefollowing actions:• Program the FOSC bits in ConfigurationWords to select the INTOSC clock source, whichwill be used as the default system clock upon adevice Reset.• Write the SCS bits in the OSCCON registerto switch the system clock source to the internaloscillator during run-time. See Section 5.3“Clock Switching”for more information.In INTOSC mode, CLKIN is available for generalpurpose I/O. CLKOUT is available for general purposeI/O or CLKOUT.The function of the CLKOUT pin is determined by theCLKOUTEN bit in Configuration Words.The internal oscillator block has two independentoscillators clock sources.1. The HFINTOSC (High-Frequency InternalOscillator) is factory calibrated and operates at16 MHz.2. The LFINTOSC (Low-Frequency InternalOscillator) is uncalibrated and operates at31 kHz.5.2.2.1 HFINTOSCThe High-Frequency Internal Oscillator (HFINTOSC) isa factory calibrated 16 MHz internal clock source.The outputs of the HFINTOSC connects to a prescalerand multiplexer (see Figure 5-1). One of multiplefrequencies derived from the HFINTOSC can beselected via software using the IRCF bits of theOSCCON register. See Section 5.2.2.4 “InternalOscillator Clock Switch Timing” for more information.The HFINTOSC is enabled by:• Configure the IRCF bits of the OSCCONregister for the desired HF frequency, and• FOSC = 00, or• Set the System Clock Source (SCS) bits of theOSCCON register to ‘1x’.A fast start-up oscillator allows internal circuits topower-up and stabilize before switching to HFINTOSC.The High-Frequency Internal Oscillator Ready bit(HFIOFR) of the OSCSTAT register indicates when theHFINTOSC is running.The High-Frequency Internal Oscillator Stable bit(HFIOFS) of the OSCSTAT register indicates when theHFINTOSC is running within 0.5% of its final value.5.2.2.2 LFINTOSCThe Low-Frequency Internal Oscillator (LFINTOSC) isan uncalibrated 31 kHz internal clock source.The output of the LFINTOSC connects to a multiplexer(see Figure 5-1). Select 31 kHz, via software, using theIRCF bits of the OSCCON register. SeeSection 5.2.2.4 “Internal Oscillator Clock SwitchTiming” for more information. The LFINTOSC is alsothe frequency for the Power-up Timer (PWRT) andWatchdog Timer (WDT).The LFINTOSC is enabled by selecting 31 kHz(IRCF bits of the OSCCON register = 000x) asthe system clock source (SCS bits of the OSCCONregister = 1x), or when any of the following areenabled:• Configure the IRCF bits of the OSCCONregister for the desired LF frequency, and• FOSC = 00, or• Set the System Clock Source (SCS) bits of theOSCCON register to ‘1x’Peripherals that use the LFINTOSC are:• Power-up Timer (PWRT)• Watchdog Timer (WDT)The Low-Frequency Internal Oscillator Ready bit(LFIOFR) of the OSCSTAT register indicates when theLFINTOSC is running. 2011 Microchip Technology Inc. Preliminary DS41615A-page 47

PIC12(L)F15015.2.2.3 Internal Oscillator FrequencySelectionThe system clock speed can be selected via softwareusing the Internal Oscillator Frequency Select bitsIRCF of the OSCCON register.The outputs of the 16 MHz HFINTOSC postscaler andthe LFINTOSC connect to a multiplexer (seeFigure 5-1). The Internal Oscillator Frequency Selectbits IRCF of the OSCCON register select thefrequency output of the internal oscillators. One of thefollowing frequencies can be selected via software:• HFINTOSC- 16 MHz- 8 MHz- 4 MHz- 2 MHz- 1 MHz- 500 kHz (default after Reset)- 250 kHz- 125 kHz- 62.5 kHz- 31.25 kHz• LFINTOSC- 31 kHzNote: Following any Reset, the IRCF bitsof the OSCCON register are set to ‘0111’and the frequency selection is set to500 kHz. The user can modify the IRCFbits to select a different frequency.The IRCF bits of the OSCCON register allowduplicate selections for some frequencies. These duplicatechoices can offer system design trade-offs. Lowerpower consumption can be obtained when changingoscillator sources for a given frequency. Faster transitiontimes can be obtained between frequency changesthat use the same oscillator source.5.2.2.4 Internal Oscillator Clock SwitchTimingWhen switching between the HFINTOSC and theLFINTOSC, the new oscillator may already be shutdown to save power (see Figure 5-3). If this is the case,there is a delay after the IRCF bits of theOSCCON register are modified before the frequencyselection takes place. The OSCSTAT register willreflect the current active status of the HFINTOSC andLFINTOSC oscillators. The sequence of a frequencyselection is as follows:1. IRCF bits of the OSCCON register aremodified.2. If the new clock is shut down, a clock start-updelay is started.3. Clock switch circuitry waits for a falling edge ofthe current clock.4. Clock switch is complete.See Figure 5-3 for more details.If the internal oscillator speed is switched between twoclocks of the same source, there is no start-up delaybefore the new frequency is selected.Start-up delay specifications are located in theoscillator tables of Section 27.0 “ElectricalSpecifications”.DS41615A-page 48 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501FIGURE 5-3:INTERNAL OSCILLATOR SWITCH TIMINGHFINTOSCLFINTOSC (WDT disabled)HFINTOSCStart-up Time 2-cycle Sync RunningLFINTOSCIRCF System Clock00HFINTOSCLFINTOSC (WDT enabled)HFINTOSCLFINTOSC2-cycle SyncRunningIRCF System Clock00LFINTOSCLFINTOSCHFINTOSCHFINTOSCLFINTOSC turns off unless WDT is enabledStart-up Time 2-cycle Sync RunningIRCF = 0 0System Clock 2011 Microchip Technology Inc. Preliminary DS41615A-page 49

PIC12(L)F15015.3 Clock SwitchingThe system clock source can be switched betweenexternal and internal clock sources via software usingthe System Clock Select (SCS) bits of the OSCCONregister. The following clock sources can be selectedusing the SCS bits:• Default system oscillator determined by FOSCbits in Configuration Words• Internal Oscillator Block (INTOSC)5.3.1 SYSTEM CLOCK SELECT (SCS)BITSThe System Clock Select (SCS) bits of the OSCCONregister selects the system clock source that is used forthe CPU and peripherals.• When the SCS bits of the OSCCON register = 00,the system clock source is determined by value ofthe FOSC bits in the Configuration Words.• When the SCS bits of the OSCCON register = 1x,the system clock source is chosen by the internaloscillator frequency selected by the IRCFbits of the OSCCON register. After a Reset, theSCS bits of the OSCCON register are alwayscleared.When switching between clock sources, a delay isrequired to allow the new clock to stabilize. These oscillatordelays are shown in Table 5-2.TABLE 5-1:OSCILLATOR SWITCHING DELAYSSwitch From Switch To Frequency Oscillator DelaySleep/PORLFINTOSCHFINTOSCEC31 kHz31.25kHz-16MHzDC – 20 MHz2 cyclesLFINTOSC EC DC – 20 MHz 1 cycle of eachAny clock source HFINTOSC 31.25 kHz-16 MHz 2 s (approx.)Any clock source LFINTOSC 31 kHz 1 cycle of eachDS41615A-page 50 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15015.4 Oscillator Control RegistersREGISTER 5-1:OSCCON: OSCILLATOR CONTROL REGISTERU-0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0— IRCF — SCSbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7 Unimplemented: Read as ‘0’bit 6-3 IRCF: Internal Oscillator Frequency Select bits1111 = 16 MHz1110 = 8 MHz1101 = 4 MHz1100 = 2 MHz1011 = 1 MHz1010 = 500 kHz (1)1001 = 250 kHz (1)1000 = 125 kHz (1)0111 = 500 kHz (default upon Reset)0110 = 250 kHz0101 = 125 kHz0100 = 62.5 kHz001x = 31.25 kHz000x = 31 kHz (LFINTOSC)bit 2 Unimplemented: Read as ‘0’bit 1-0 SCS: System Clock Select bits1x = Internal oscillator block01 = Reserved00 = Clock determined by FOSC in Configuration WordsNote 1: Duplicate frequency derived from HFINTOSC. 2011 Microchip Technology Inc. Preliminary DS41615A-page 51

PIC12(L)F1501REGISTER 5-2:OSCSTAT: OSCILLATOR STATUS REGISTERU-0 U-0 U-0 R-0/q U-0 U-0 R-0/q R-0/q— — — HFIOFR — — LFIOFR HFIOFSbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditionalbit 7-5 Unimplemented: Read as ‘0’bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit1 = 16 MHz Internal Oscillator (HFINTOSC) is ready0 = 16 MHz Internal Oscillator (HFINTOSC) is not readybit 3-2 Unimplemented: Read as ‘0’bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit1 = 31 kHz Internal Oscillator (LFINTOSC) is ready0 = 31 kHz Internal Oscillator (LFINTOSC) is not readybit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit1 = 16 MHz Internal Oscillator (HFINTOSC) is stable0 = 16 MHz Internal Oscillator (HFINTOSC) is not yet stableTABLE 5-2:SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCESName Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Registeron PageOSCCON — IRCF — SCS 51OSCSTAT — — — HFIOFR — — LFIOFR HFIOFS 52Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.TABLE 5-3:SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCESName Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0Registeron PageCONFIG1Legend:13:8 — — — — CLKOUTEN BOREN —7:0 CP MCLRE PWRTE WDTE — FOSC— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.40DS41615A-page 52 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15016.0 RESETSThere are multiple ways to reset this device:• Power-on Reset (POR)• Brown-out Reset (BOR)• Low-Power Brown-out Reset (LPBOR)• MCLR Reset• WDT Reset• RESET instruction• Stack Overflow• Stack Underflow• Programming mode exitTo allow VDD to stabilize, an optional Power-up Timercan be enabled to extend the Reset time after a BORor POR event.A simplified block diagram of the On-chip Reset Circuitis shown in Figure 6-1.FIGURE 6-1:SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUITICSP Programming Mode ExitRESET InstructionStackPointerMCLRSleepMCLREVDDWDTTime-outPower-onResetDeviceResetBrown-outResetRPWRTDoneLPBORResetLFINTOSCPWRTEBORActive (1)Note 1: See Table 6-1 for BOR active conditions. 2011 Microchip Technology Inc. Preliminary DS41615A-page 53

PIC12(L)F15016.1 Power-on Reset (POR)The POR circuit holds the device in Reset until VDD hasreached an acceptable level for minimum operation.Slow rising VDD, fast operating speeds or analogperformance may require greater than minimum VDD.The PWRT, BOR or MCLR features can be used toextend the start-up period until all device operationconditions have been met.6.1.1 POWER-UP TIMER (PWRT)The Power-up Timer provides a nominal 64 mstime-out on POR or Brown-out Reset.The device is held in Reset as long as PWRT is active.The PWRT delay allows additional time for the VDD torise to an acceptable level. The Power-up Timer isenabled by clearing the PWRTE bit in ConfigurationWords.The Power-up Timer starts after the release of the PORand BOR.For additional information, refer to Application NoteAN607, “Power-up Trouble Shooting” (DS00607).6.2 Brown-Out Reset (BOR)The BOR circuit holds the device in Reset when VDDreaches a selectable minimum level. Between thePOR and BOR, complete voltage range coverage forexecution protection can be implemented.The Brown-out Reset module has four operatingmodes controlled by the BOREN bits in ConfigurationWords. The four operating modes are:• BOR is always on• BOR is off when in Sleep• BOR is controlled by software• BOR is always offRefer to Table 6-1 for more information.The Brown-out Reset voltage level is selectable byconfiguring the BORV bit in Configuration Words.A VDD noise rejection filter prevents the BOR from triggeringon small events. If VDD falls below VBOR for aduration greater than parameter TBORDC, the devicewill reset. See Figure 6-2 for more information.TABLE 6-1:BOR OPERATING MODESBOREN SBOREN Device Mode BOR ModeInstruction Execution upon:Release of POR or Wake-up from Sleep11 X X Active Waits for BOR ready (1) (BORRDY = 1)10 X01AwakeSleepActiveDisabledWaits for BOR ready (BORRDY = 1)1 X Active Waits for BOR ready (1) (BORRDY = 1)0 X Disabled00 X X DisabledBegins immediately (BORRDY = x)Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BORready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BORcircuit is forced on by the BOREN bits.6.2.1 BOR IS ALWAYS ONWhen the BOREN bits of Configuration Words are programmedto ‘11’, the BOR is always on. The devicestart-up will be delayed until the BOR is ready and VDDis higher than the BOR threshold.BOR protection is active during Sleep. The BOR doesnot delay wake-up from Sleep.6.2.2 BOR IS OFF IN SLEEPWhen the BOREN bits of Configuration Words are programmedto ‘10’, the BOR is on, except in Sleep. Thedevice start-up will be delayed until the BOR is readyand VDD is higher than the BOR threshold.BOR protection is not active during Sleep. The devicewake-up will be delayed until the BOR is ready.6.2.3 BOR CONTROLLED BY SOFTWAREWhen the BOREN bits of Configuration Words areprogrammed to ‘01’, the BOR is controlled by theSBOREN bit of the BORCON register. The devicestart-up is not delayed by the BOR ready condition orthe VDD level.BOR protection begins as soon as the BOR circuit isready. The status of the BOR circuit is reflected in theBORRDY bit of the BORCON register.BOR protection is unchanged by Sleep.DS41615A-page 54 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501FIGURE 6-2: BROWN-OUT SITUATIONSVDDVBORInternalResetTPWRT (1)VDDVBORInternal< TPWRTReset TPWRT (1)VDDVBORInternalResetTPWRT (1)Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.REGISTER 6-1:BORCON: BROWN-OUT RESET CONTROL REGISTERR/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/uSBOREN BORFS — — — — — BORRDYbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on conditionbit 7SBOREN: Software Brown-out Reset Enable bitIf BOREN in Configuration Words 01:SBOREN is read/write, but has no effect on the BOR.If BOREN in Configuration Words = 01:1 = BOR Enabled0 = BOR Disabledbit 6 BORFS: Brown-out Reset Fast Start bit (1)If BOREN = 11 (Always on) or BOREN = 00 (Always off)BORFS is Read/Write, but has no effect.If BOREN = 10 (Disabled in Sleep) or BOREN = 01 (Under software control):1 = Band gap is forced on always (covers sleep/wake-up/operating cases)0 = Band gap operates normally, and may turn offbit 5-1 Unimplemented: Read as ‘0’bit 0BORRDY: Brown-out Reset Circuit Ready Status bit1 = The Brown-out Reset circuit is active0 = The Brown-out Reset circuit is inactiveNote 1:BOREN bits are located in Configuration Words. 2011 Microchip Technology Inc. Preliminary DS41615A-page 55

PIC12(L)F15016.3 Low-Power Brown-out Reset(LPBOR)The Low-Power Brown-Out Reset (LPBOR) is anessential part of the Reset subsystem. Refer toFigure 6-1 to see how the BOR interacts with othermodules.The LPBOR is used to monitor the external VDD pin.When too low of a voltage is detected, the device isheld in Reset. When this occurs, a register bit (BOR) ischanged to indicate that a BOR Reset has occurred.The same bit is set for both the BOR and the LPBOR.Refer to Register 6-2.6.3.1 ENABLING LPBORThe LPBOR is controlled by the LPBOR bit ofConfiguration Words. When the device is erased, theLPBOR module defaults to disabled.6.3.1.1 LPBOR Module OutputThe output of the LPBOR module is a signal indicatingwhether or not a Reset is to be asserted. This signal isOR’d together with the Reset signal of the BOR moduleto provide the generic BOR signal which goes tothe PCON register and to the power control block.6.4 MCLRThe MCLR is an optional external input that can resetthe device. The MCLR function is controlled by theMCLRE bit of Configuration Words and the LVP bit ofConfiguration Words (Table 6-2).TABLE 6-2:6.4.1 MCLR ENABLEDMCLR CONFIGURATIONMCLRE LVP MCLRWhen MCLR is enabled and the pin is held low, thedevice is held in Reset. The MCLR pin is connected toVDD through an internal weak pull-up.The device has a noise filter in the MCLR Reset path.The filter will detect and ignore small pulses.Note:0 0 Disabled1 0 Enabledx 1 EnabledA Reset does not drive the MCLR pin low.6.4.2 MCLR DISABLEDWhen MCLR is disabled, the pin functions as a generalpurpose input and the internal weak pull-up is undersoftware control. See Section 11.2 “PORTA Registers”for more information.6.5 Watchdog Timer (WDT) ResetThe Watchdog Timer generates a Reset if the firmwaredoes not issue a CLRWDT instruction within the time-outperiod. The TO and PD bits in the STATUS register arechanged to indicate the WDT Reset. See Section 9.0“Watchdog Timer” for more information.6.6 RESET InstructionA RESET instruction will cause a device Reset. The RIbit in the PCON register will be set to ‘0’. See Table 6-4for default conditions after a RESET instruction hasoccurred.6.7 Stack Overflow/Underflow ResetThe device can reset when the Stack Overflows orUnderflows. The STKOVF or STKUNF bits of the PCONregister indicate the Reset condition. These Resets areenabled by setting the STVREN bit in ConfigurationWords. See Section 3.4.2 “Overflow/UnderflowReset” for more information.6.8 Programming Mode ExitUpon exit of Programming mode, the device willbehave as if a POR had just occurred.6.9 Power-Up TimerThe Power-up Timer optionally delays device executionafter a BOR or POR event. This timer is typically used toallow VDD to stabilize before allowing the device to startrunning.The Power-up Timer is controlled by the PWRTE bit ofConfiguration Words.6.10 Start-up SequenceUpon the release of a POR or BOR, the following mustoccur before the device will begin executing:1. Power-up Timer runs to completion (if enabled).2. MCLR must be released (if enabled).The total time-out will vary based on oscillator configurationand Power-up Timer configuration. SeeSection 5.0 “Oscillator Module” for more information.The Power-up Timer runs independently of MCLRReset. If MCLR is kept low long enough, the Power-upTimer will expire. Upon bringing MCLR high, the devicewill begin execution immediately (see Figure 6-3). Thisis useful for testing purposes or to synchronize morethan one device operating in parallel.DS41615A-page 56 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501FIGURE 6-3:RESET START-UP SEQUENCEVDDInternal PORPower-Up TimerTPWRTMCLRInternal RESETTMCLRInternal OscillatorOscillatorFOSCExternal Clock (EC)CLKINFOSC 2011 Microchip Technology Inc. Preliminary DS41615A-page 57

PIC12(L)F15016.11 Determining the Cause of a ResetUpon any Reset, multiple bits in the STATUS andPCON registers are updated to indicate the cause ofthe Reset. Table 6-3 and Table 6-4 show the Resetconditions of these registers.TABLE 6-3:RESET STATUS BITS AND THEIR SIGNIFICANCESTKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition0 0 1 1 1 0 x 1 1 Power-on Reset0 0 1 1 1 0 x 0 x Illegal, TO is set on POR0 0 1 1 1 0 x x 0 Illegal, PD is set on POR0 0 u 1 1 u 0 1 1 Brown-out Resetu u 0 u u u u 0 u WDT Resetu u u u u u u 0 0 WDT Wake-up from Sleepu u u u u u u 1 0 Interrupt Wake-up from Sleepu u u 0 u u u u u MCLR Reset during normal operationu u u 0 u u u 1 0 MCLR Reset during Sleepu u u u 0 u u u u RESET Instruction Executed1 u u u u u u u u Stack Overflow Reset (STVREN = 1)u 1 u u u u u u u Stack Underflow Reset (STVREN = 1)TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS (2)ConditionProgramCounterSTATUSRegisterPCONRegisterPower-on Reset 0000h ---1 1000 00-- 110xMCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuuMCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuuWDT Reset 0000h ---0 uuuu uu-- uuuuWDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuuBrown-out Reset 0000h ---1 1uuu 00-- 11u0Interrupt Wake-up from Sleep PC + 1 (1) ---1 0uuu uu-- uuuuRESET Instruction Executed 0000h ---u uuuu uu-- u0uuStack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuuStack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuuLegend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.Note 1: When the wake-up is due to an interrupt and the Global Interrupt Enable bit (GIE) is set, the return addressis pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.2: If a Status bit is not implemented, that bit will be read as ‘0’.DS41615A-page 58 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15016.12 Power Control (PCON) RegisterThe Power Control (PCON) register contains flag bitsto differentiate between a:• Power-on Reset (POR)• Brown-out Reset (BOR)• Reset Instruction Reset (RI)• MCLR Reset (RMCLR)• Watchdog Timer Reset (RWDT)• Stack Underflow Reset (STKUNF)• Stack Overflow Reset (STKOVF)The PCON register bits are shown in Register 6-2.REGISTER 6-2:PCON: POWER CONTROL REGISTERR/W/HS-0/q R/W/HS-0/q U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/uSTKOVF STKUNF — RWDT RMCLR RI POR BORbit 7 bit 0Legend:HC = Bit is cleared by hardwareHS = Bit is set by hardwareR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on conditionbit 7STKOVF: Stack Overflow Flag bit1 = A Stack Overflow occurred0 = A Stack Overflow has not occurred or cleared by firmwarebit 6STKUNF: Stack Underflow Flag bit1 = A Stack Underflow occurred0 = A Stack Underflow has not occurred or cleared by firmwarebit 5 Unimplemented: Read as ‘0’bit 4bit 3bit 2bit 1bit 0RWDT: Watchdog Timer Reset Flag bit1 = A Watchdog Timer Reset has not occurred or set by firmware0 = A Watchdog Timer Reset has occurred (cleared by hardware)RMCLR: MCLR Reset Flag bit1 = A MCLR Reset has not occurred or set by firmware0 = A MCLR Reset has occurred (cleared by hardware)RI: RESET Instruction Flag bit1 = A RESET instruction has not been executed or set by firmware0 = A RESET instruction has been executed (cleared by hardware)POR: Power-on Reset Status bit1 = No Power-on Reset occurred0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)BOR: Brown-out Reset Status bit1 = No Brown-out Reset occurred0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Resetoccurs) 2011 Microchip Technology Inc. Preliminary DS41615A-page 59

PIC12(L)F1501TABLE 6-5:SUMMARY OF REGISTERS ASSOCIATED WITH RESETSName Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Registeron PageBORCON SBOREN BORFS — — — — — BORRDY 55PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 59STATUS — — — TO PD Z DC C 18WDTCON — — WDTPS SWDTEN 81Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.TABLE 6-6:SUMMARY OF CONFIGURATION WORD WITH RESETSName Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0Registeron PageCONFIG1 13:8 — — — — CLKOUTEN BOREN — 407:0 CP MCLRE PWRTE WDTE — FOSCCONFIG2 13:8 — — LVP — LPBOR BORV STVREN — 417:0 — — — — — — WRTLegend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.DS41615A-page 60 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15017.0 INTERRUPTSThe interrupt feature allows certain events to preemptnormal program flow. Firmware is used to determinethe source of the interrupt and act accordingly. Someinterrupts can be configured to wake the MCU fromSleep mode.This chapter contains the following information forInterrupts:• Operation• Interrupt Latency• Interrupts During Sleep• INT Pin• Automatic Context SavingMany peripherals produce interrupts. Refer to thecorresponding chapters for details.A block diagram of the interrupt logic is shown inFigure 7-1.FIGURE 7-1:INTERRUPT LOGICPeripheral Interrupts(TMR1IF) PIR1(TMR1IF) PIR1TMR0IFTMR0IEINTFINTEIOCIFIOCIEWake-up(If in Sleep mode)Interruptto CPUPIRnPIEnPEIEGIE 2011 Microchip Technology Inc. Preliminary DS41615A-page 61

PIC12(L)F15017.1 OperationInterrupts are disabled upon any device Reset. Theyare enabled by setting the following bits:• GIE bit of the INTCON register• Interrupt Enable bit(s) for the specific interruptevent(s)• PEIE bit of the INTCON register (if the InterruptEnable bit of the interrupt event is contained in thePIE1, PIE2 and PIE3 registers)The INTCON, PIR1, PIR2 and PIR3 registers recordindividual interrupts via interrupt flag bits. Interrupt flagbits will be set, regardless of the status of the GIE, PEIEand individual interrupt enable bits.The following events happen when an interrupt eventoccurs while the GIE bit is set:• Current prefetched instruction is flushed• GIE bit is cleared• Current Program Counter (PC) is pushed onto thestack• Critical registers are automatically saved to theshadow registers (See “Section 7.5 “AutomaticContext Saving”.”)• PC is loaded with the interrupt vector 0004hThe firmware within the Interrupt Service Routine (ISR)should determine the source of the interrupt by pollingthe interrupt flag bits. The interrupt flag bits must becleared before exiting the ISR to avoid repeatedinterrupts. Because the GIE bit is cleared, any interruptthat occurs while executing the ISR will be recordedthrough its interrupt flag, but will not cause theprocessor to redirect to the interrupt vector.The RETFIE instruction exits the ISR by popping theprevious address from the stack, restoring the savedcontext from the shadow registers and setting the GIEbit.For additional information on a specific interrupt’soperation, refer to its peripheral chapter.Note 1: Individual interrupt flag bits are set,regardless of the state of any otherenable bits.2: All interrupts will be ignored while the GIEbit is cleared. Any interrupt occurringwhile the GIE bit is clear will be servicedwhen the GIE bit is set again.7.2 Interrupt LatencyInterrupt latency is defined as the time from when theinterrupt event occurs to the time code execution at theinterrupt vector begins. The latency for synchronousinterrupts is 3 or 4 instruction cycles. For asynchronousinterrupts, the latency is 3 to 5 instruction cycles,depending on when the interrupt occurs. See Figure 7-2and Figure 7.3 for more details.DS41615A-page 62 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501FIGURE 7-2:INTERRUPT LATENCYFoscQ1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4CLKRInterrupt Sampledduring Q1InterruptGIEPCPC-1PC PC+10004h 0005hExecute1 Cycle Instruction at PCInst(PC)NOPNOPInst(0004h)InterruptGIEPCPC-1PCPC+1/FSRADDRNew PC/PC+10004h0005hExecute2 Cycle Instruction at PCInst(PC)NOPNOPInst(0004h)InterruptGIEPCPC-1PCFSR ADDR PC+1 PC+2 0004h 0005hExecute3 Cycle Instruction at PCINST(PC)NOPNOPNOPInst(0004h)Inst(0005h)InterruptGIEPCPC-1PCFSR ADDR PC+1 PC+2 0004h 0005hExecute3 Cycle Instruction at PCINST(PC)NOPNOPNOPNOPInst(0004h) 2011 Microchip Technology Inc. Preliminary DS41615A-page 63

PIC12(L)F1501FIGURE 7-3:INT PIN INTERRUPT TIMINGQ1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4FOSCCLKOUT(3)INT pinINTF(1)(4)(1)(2)Interrupt LatencyGIEINSTRUCTION FLOWPCInstructionFetchedPC PC + 1 PC + 1 0004h 0005hInst (PC) Inst (PC + 1)—Inst (0004h)Inst (0005h)InstructionExecutedInst (PC – 1)Inst (PC)Forced NOPForced NOPInst (0004h)Note 1:INTF flag is sampled here (every Q1).2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.3: For minimum width of INT pulse, refer to AC specifications in Section 27.0 “Electrical Specifications””.4: INTF is enabled to be set any time during the Q4-Q1 cycles.DS41615A-page 64 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15017.3 Interrupts During SleepSome interrupts can be used to wake from Sleep. Towake from Sleep, the peripheral must be able tooperate without the system clock. The interrupt sourcemust have the appropriate Interrupt Enable bit(s) setprior to entering Sleep.On waking from Sleep, if the GIE bit is also set, theprocessor will branch to the interrupt vector. Otherwise,the processor will continue executing instructions afterthe SLEEP instruction. The instruction directly after theSLEEP instruction will always be executed beforebranching to the ISR. Refer to Section 8.0“Power-Down Mode (Sleep)” for more details.7.4 INT PinThe INT pin can be used to generate an asynchronousedge-triggered interrupt. This interrupt is enabled bysetting the INTE bit of the INTCON register. TheINTEDG bit of the OPTION_REG register determines onwhich edge the interrupt will occur. When the INTEDGbit is set, the rising edge will cause the interrupt. Whenthe INTEDG bit is clear, the falling edge will cause theinterrupt. The INTF bit of the INTCON register will be setwhen a valid edge appears on the INT pin. If the GIE andINTE bits are also set, the processor will redirectprogram execution to the interrupt vector.7.5 Automatic Context SavingUpon entering an interrupt, the return PC address issaved on the stack. Additionally, the following registersare automatically saved in the Shadow registers:• W register• STATUS register (except for TO and PD)• BSR register• FSR registers• PCLATH registerUpon exiting the Interrupt Service Routine, these registersare automatically restored. Any modifications tothese registers during the ISR will be lost. If modificationsto any of these registers are desired, the correspondingShadow register should be modified and thevalue will be restored when exiting the ISR. TheShadow registers are available in Bank 31 and arereadable and writable. Depending on the user’s application,other registers may also need to be saved. 2011 Microchip Technology Inc. Preliminary DS41615A-page 65

PIC12(L)F15017.6 Interrupt Control Registers7.6.1 INTCON REGISTERThe INTCON register is a readable and writableregister, that contains the various enable and flag bitsfor TMR0 register overflow, interrupt-on-change andexternal INT pin interrupts.Note:Interrupt flag bits are set when an interruptcondition occurs, regardless of the state ofits corresponding enable bit or the GlobalInterrupt Enable bit, GIE, of the INTCONregister. User software should ensure theappropriate interrupt flag bits are clearprior to enabling an interrupt.REGISTER 7-1:INTCON: INTERRUPT CONTROL REGISTERR/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF (1)bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7bit 6bit 5bit 4bit 3bit 2GIE: Global Interrupt Enable bit1 = Enables all active interrupts0 = Disables all interruptsPEIE: Peripheral Interrupt Enable bit1 = Enables all active peripheral interrupts0 = Disables all peripheral interruptsTMR0IE: Timer0 Overflow Interrupt Enable bit1 = Enables the Timer0 interrupt0 = Disables the Timer0 interruptINTE: INT External Interrupt Enable bit1 = Enables the INT external interrupt0 = Disables the INT external interruptIOCIE: Interrupt-on-Change Enable bit1 = Enables the interrupt-on-change0 = Disables the interrupt-on-changeTMR0IF: Timer0 Overflow Interrupt Flag bit1 = TMR0 register has overflowed0 = TMR0 register did not overflowbit 1INTF: INT External Interrupt Flag bit1 = The INT external interrupt occurred0 = The INT external interrupt did not occurbit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit (1)1 = When at least one of the interrupt-on-change pins changed state0 = None of the interrupt-on-change pins have changed stateNote 1:The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCBF registerhave been cleared by software.DS41615A-page 66 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15017.6.2 PIE1 REGISTERThe PIE1 register contains the interrupt enable bits, asshown in Register 7-2.Note:Bit PEIE of the INTCON register must beset to enable any peripheral interrupt.REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0TMR1GIE ADIE — — — — TMR2IE TMR1IEbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7TMR1GIE: Timer1 Gate Interrupt Enable bit1 = Enables the Timer1 Gate Acquisition interrupt0 = Disables the Timer1 Gate Acquisition interruptbit 6ADIE: A/D Converter (ADC) Interrupt Enable bit1 = Enables the ADC interrupt0 = Disables the ADC interruptbit 5-2 Unimplemented: Read as ‘0’bit 1bit 0TMR2IE: TMR2 to PR2 Match Interrupt Enable bit1 = Enables the Timer2 to PR2 match interrupt0 = Disables the Timer2 to PR2 match interruptTMR1IE: Timer1 Overflow Interrupt Enable bit1 = Enables the Timer1 overflow interrupt0 = Disables the Timer1 overflow interrupt 2011 Microchip Technology Inc. Preliminary DS41615A-page 67

PIC12(L)F15017.6.3 PIE2 REGISTERThe PIE2 register contains the interrupt enable bits, asshown in Register 7-3.Note:Bit PEIE of the INTCON register must beset to enable any peripheral interrupt.REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2U-0 U-0 R/W-0/0 U-0 U-0 R/W-0/0 U-0 U-0— — C1IE — — NCO1IE — —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-6 Unimplemented: Read as ‘0’bit 5C1IE: Comparator C1 Interrupt Enable bit1 = Enables the Comparator C1 interrupt0 = Disables the Comparator C1 interruptbit 4-3 Unimplemented: Read as ‘0’bit 2NCO1IE: Numerically Controlled Oscillator Interrupt Enable bit1 = Enables the NCO interrupt0 = Disables the NCO interruptbit 1-0 Unimplemented: Read as ‘0’DS41615A-page 68 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15017.6.4 PIE3 REGISTERThe PIE3 register contains the interrupt enable bits, asshown in Register 7-4.Note:Bit PEIE of the INTCON register must beset to enable any peripheral interrupt.REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0— — — — — — CLC2IE CLC1IEbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-2 Unimplemented: Read as ‘0’bit 1CLC2IE: Configurable Logic Block 2 Interrupt Enable bit1 = Enables the CLC 2 interrupt0 = Disables the CLC 2 interruptbit 0CLC1IE: Configurable Logic Block 1 Interrupt Enable bit1 = Enables the CLC 1 interrupt0 = Disables the CLC 1 interrupt 2011 Microchip Technology Inc. Preliminary DS41615A-page 69

PIC12(L)F15017.6.5 PIR1 REGISTERThe PIR1 register contains the interrupt flag bits, asshown in Register 7-5.Note:Interrupt flag bits are set when an interruptcondition occurs, regardless of the state ofits corresponding enable bit or the GlobalInterrupt Enable bit, GIE, of the INTCONregister. User software should ensure theappropriate interrupt flag bits are clear priorto enabling an interrupt.REGISTER 7-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0TMR1GIF ADIF — — — — TMR2IF TMR1IFbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7TMR1GIF: Timer1 Gate Interrupt Flag bit1 = Interrupt is pending0 = Interrupt is not pendingbit 6ADIF: A/D Converter Interrupt Flag bit1 = Interrupt is pending0 = Interrupt is not pendingbit 5-2 Unimplemented: Read as ‘0’bit 1bit 0TMR2IF: Timer2 to PR2 Interrupt Flag bit1 = Interrupt is pending0 = Interrupt is not pendingTMR1IF: Timer1 Overflow Interrupt Flag bit1 = Interrupt is pending0 = Interrupt is not pendingDS41615A-page 70 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15017.6.6 PIR2 REGISTERThe PIR2 register contains the interrupt flag bits, asshown in Register 7-6.Note:Interrupt flag bits are set when an interruptcondition occurs, regardless of the state ofits corresponding enable bit or the GlobalInterrupt Enable bit, GIE, of the INTCONregister. User software should ensure theappropriate interrupt flag bits are clear priorto enabling an interrupt.REGISTER 7-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2U-0 U-0 R/W-0/0 U-0 U-0 R/W-0/0 U-0 U-0— — C1IF — — NCO1IF — —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-6 Unimplemented: Read as ‘0’bit 5C1IF: Numerically Controlled Oscillator Flag bit1 = Interrupt is pending0 = Interrupt is not pendingbit 4-3 Unimplemented: Read as ‘0’bit 2NCO1IF: Numerically Controlled Oscillator Flag bit1 = Interrupt is pending0 = Interrupt is not pendingbit 1-0 Unimplemented: Read as ‘0’ 2011 Microchip Technology Inc. Preliminary DS41615A-page 71

PIC12(L)F15017.6.7 PIR3 REGISTERThe PIR3 register contains the interrupt flag bits, asshown in Register 7-7.Note:Interrupt flag bits are set when an interruptcondition occurs, regardless of the state ofits corresponding enable bit or the GlobalEnable bit, GIE, of the INTCON register.User software should ensure theappropriate interrupt flag bits are clear priorto enabling an interrupt.REGISTER 7-7: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0— — — — — — CLC2IF CLC1IFbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-2 Unimplemented: Read as ‘0’bit 1CLC2IF: Configurable Logic Block 2 Interrupt Flag bit1 = Interrupt is pending0 = Interrupt is not pendingbit 0CLC1IF: Configurable Logic Block 1 Interrupt Flag bit1 = Interrupt is pending0 = Interrupt is not pendingDS41615A-page 72 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501TABLE 7-1:SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTSName Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Registeron PageINTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS 143PIE1 TMR1GIE ADIE — — — — TMR2IE TMR1IE 67PIE2 — — C1IE — — NCO1IE — — 68PIE3 — — — — — — CLC2IE CLC1IE 69PIR1 TMR1GIF ADIF — — — — TMR2IF TMR1IF 70PIR2 — — C1IF — — NCO1IF — — 71PIR3 — — — — — — CLC2IF CLC1IF 72Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupts. 2011 Microchip Technology Inc. Preliminary DS41615A-page 73

PIC12(L)F1501NOTES:DS41615A-page 74 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15018.0 POWER-DOWN MODE (SLEEP)The Power-Down mode is entered by executing aSLEEP instruction.Upon entering Sleep mode, the following conditions exist:1. WDT will be cleared but keeps running, ifenabled for operation during Sleep.2. PD bit of the STATUS register is cleared.3. TO bit of the STATUS register is set.4. CPU clock is disabled.5. 31 kHz LFINTOSC is unaffected and peripheralsthat operate from it may continue operation inSleep.6. ADC is unaffected, if the dedicated FRC clock isselected.7. I/O ports maintain the status they had beforeSLEEP was executed (driving high, low orhigh-impedance).8. Resets other than WDT are not affected bySleep mode.Refer to individual chapters for more details onperipheral operation during Sleep.To minimize current consumption, the followingconditions should be considered:• I/O pins should not be floating• External circuitry sinking current from I/O pins• Internal circuitry sourcing current from I/O pins• Current draw from pins with internal weak pull-ups• Modules using 31 kHz LFINTOSC• CWG, NCO and CLC modules using HFINTOSCI/O pins that are high-impedance inputs should bepulled to VDD or VSS externally to avoid switchingcurrents caused by floating inputs.Examples of internal circuitry that might be sourcingcurrent include the FVR module. See Section 13.0“Fixed Voltage Reference (FVR)” for moreinformation on this module.8.1 Wake-up from SleepThe device can wake-up from Sleep through one of thefollowing events:1. External Reset input on MCLR pin, if enabled2. BOR Reset, if enabled3. POR Reset4. Watchdog Timer, if enabled5. Any external interrupt6. Interrupts by peripherals capable of running duringSleep (see individual peripheral for moreinformation)The first three events will cause a device Reset. Thelast three events are considered a continuation of programexecution. To determine whether a device Resetor wake-up event occurred, refer to Section 6.11“Determining the Cause of a Reset”.When the SLEEP instruction is being executed, the nextinstruction (PC + 1) is prefetched. For the device towake-up through an interrupt event, the correspondinginterrupt enable bit must be enabled. Wake-up willoccur regardless of the state of the GIE bit. If the GIEbit is disabled, the device continues execution at theinstruction after the SLEEP instruction. If the GIE bit isenabled, the device executes the instruction after theSLEEP instruction, the device will then call the InterruptService Routine. In cases where the execution of theinstruction following SLEEP is not desirable, the usershould have a NOP after the SLEEP instruction.The WDT is cleared when the device wakes up fromSleep, regardless of the source of wake-up.8.1.1 WAKE-UP USING INTERRUPTSWhen global interrupts are disabled (GIE cleared) andany interrupt source has both its interrupt enable bitand interrupt flag bit set, one of the following will occur:• If the interrupt occurs before the execution of aSLEEP instruction:- SLEEP instruction will execute as a NOP.- WDT and WDT prescaler will not be cleared- TO bit of the STATUS register will not be set- PD bit of the STATUS register will not becleared.• If the interrupt occurs during or after the executionof a SLEEP instruction:- SLEEP instruction will be completely executed- Device will immediately wake-up from Sleep- WDT and WDT prescaler will be cleared- TO bit of the STATUS register will be set- PD bit of the STATUS register will be cleared 2011 Microchip Technology Inc. Preliminary DS41615A-page 75

PIC12(L)F1501Even if the flag bits were checked before executing aSLEEP instruction, it may be possible for flag bits tobecome set before the SLEEP instruction completes. Todetermine whether a SLEEP instruction executed, testthe PD bit. If the PD bit is set, the SLEEP instructionwas executed as a NOP.FIGURE 8-1:WAKE-UP FROM SLEEP THROUGH INTERRUPTCLKIN (1)CLKOUT (2)Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Interrupt flagGIE bit(INTCON reg.)Processor inSleepInterrupt Latency (3)Instruction FlowPCInstructionFetchedInstructionExecutedPC PC + 1 PC + 2Inst(PC) = SleepInst(PC - 1)Inst(PC + 1)SleepPC + 2Inst(PC + 2)Inst(PC + 1)PC + 2 0004h 0005hInst(0004h) Inst(0005h)Forced NOP Forced NOP Inst(0004h)Note 1: External clock. High, Medium, Low mode assumed.2: CLKOUT is shown here for timing reference.3: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.DS41615A-page 76 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15018.2 Low-Power Sleep ModeThe PIC12F1501 device contains an internal LowDropout (LDO) voltage regulator, which allows thedevice I/O pins to operate at voltages up to 5.5V whilethe internal device logic operates at a lower voltage.The LDO and its associated reference circuitry mustremain active when the device is in Sleep mode. ThePIC12F1501 allows the user to optimize the operatingcurrent in Sleep, depending on the applicationrequirements.A Low-Power Sleep mode can be selected by settingthe VREGPM bit of the VREGCON register. With thisbit set, the LDO and reference circuitry are placed in alow-power state when the device is in Sleep.8.2.1 SLEEP CURRENT VS. WAKE-UPTIMEIn the default operating mode, the LDO and referencecircuitry remain in the normal configuration while inSleep. The device is able to exit Sleep mode quicklysince all circuits remain active. In Low-Power Sleepmode, when waking up from Sleep, an extra delay timeis required for these circuits to return to the normal configurationand stabilize.The Low-Power Sleep mode is beneficial for applicationsthat stay in Sleep mode for long periods of time.The Normal mode is beneficial for applications thatneed to wake from Sleep quickly and frequently.8.2.2 PERIPHERAL USAGE IN SLEEPSome peripherals that can operate in Sleep mode willnot operate properly with the Low-Power Sleep modeselected. The LDO will remain in the Normal Powermode when those peripherals are enabled. TheLow-Power Sleep mode is intended for use with theseperipherals:• Brown-Out Reset (BOR)• Watchdog Timer (WDT)• External interrupt pin/Interrupt-on-change pins• Timer1 (with external clock source)The Complementary Waveform Generator (CWG), theNumerically Controlled Oscillator (NCO) and the ConfigurableLogic Cell (CLC) modules can utilize theHFINTOSC oscillator as either a clock source or as aninput source. Under certain conditions, when theHFINTOSC is selected for use with the CWG, NCO orCLC modules, the HFINTOSC will remain active duringSleep. This will have a direct effect on the Sleep modecurrent.Please refer to sections 22.5 “Operation DuringSleep”, 23.7 “Operation In Sleep” and 24.10 “OperationDuring Sleep” for more information.Note:The PIC12LF1501 does not have a configurableLow-Power Sleep mode.PIC12LF1501 is an unregulated deviceand is always in the lowest power statewhen in Sleep, with no wake-up time penalty.This device has a lower maximumVDD and I/O voltage than thePIC12F1501. See Section 25.0 “ElectricalSpecifications” for more information. 2011 Microchip Technology Inc. Preliminary DS41615A-page 77

PIC12(L)F1501REGISTER 8-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER (1)U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1— — — — — — VREGPM Reservedbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-2 Unimplemented: Read as ‘0’bit 1VREGPM: Voltage Regulator Power Mode Selection bit1 = Low-Power Sleep mode enabled in SleepDraws lowest current in Sleep, slower wake-up0 = Normal Power mode enabled in SleepDraws higher current in Sleep, faster wake-upbit 0Reserved: Read as ‘1’. Maintain this bit set.Note 1:PIC12F1501 only.TABLE 8-1:SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODEName Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Register onPageINTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 107IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 107IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 107PIE1 TMR1GIE ADIE — — — — TMR2IE TMR1IE 67PIE2 — — C1IE — — NCO1IE — — 68PIE3 — — — — — — CLC2IE CLC1IE 69PIR1 TMR1GIF ADIF — — — — TMR2IF TMR1IF 70PIR2 — — C1IF — — NCO1IF — — 71PIR3 — — — — — — CLC2IF CLC1IF 72STATUS — — — TO PD Z DC C 18WDTCON — — WDTPS SWDTEN 81Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode.DS41615A-page 78 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15019.0 WATCHDOG TIMERThe Watchdog Timer is a system timer that generatesa Reset if the firmware does not issue a CLRWDTinstruction within the time-out period. The WatchdogTimer is typically used to recover the system fromunexpected events.The WDT has the following features:• Independent clock source• Multiple operating modes- WDT is always on- WDT is off when in Sleep- WDT is controlled by software- WDT is always off• Configurable time-out period is from 1 ms to 256seconds (typical)• Multiple Reset conditions• Operation during SleepFIGURE 9-1:WATCHDOG TIMER BLOCK DIAGRAMWDTE = 01SWDTENWDTE = 11WDTE = 10LFINTOSC23-bit ProgrammablePrescaler WDTWDT Time-outSleepWDTPS 2011 Microchip Technology Inc. Preliminary DS41615A-page 79

PIC12(L)F15019.1 Independent Clock SourceThe WDT derives its time base from the 31 kHzLFINTOSC internal oscillator. Time intervals in thischapter are based on a nominal interval of 1 ms. SeeSection 27.0 “Electrical Specifications” for theLFINTOSC tolerances.9.2 WDT Operating ModesThe Watchdog Timer module has four operating modescontrolled by the WDTE bits in ConfigurationWords. See Table 9-1.9.2.1 WDT IS ALWAYS ONWhen the WDTE bits of Configuration Words are set to‘11’, the WDT is always on.WDT protection is active during Sleep.9.2.2 WDT IS OFF IN SLEEPWhen the WDTE bits of Configuration Words are set to‘10’, the WDT is on, except in Sleep.WDT protection is not active during Sleep.9.2.3 WDT CONTROLLED BY SOFTWAREWhen the WDTE bits of Configuration Words are set to‘01’, the WDT is controlled by the SWDTEN bit of theWDTCON register.WDT protection is unchanged by Sleep. See Table 9-1for more details.TABLE 9-1:WDT OPERATING MODES9.3 Time-Out PeriodThe WDTPS bits of the WDTCON register set thetime-out period from 1 ms to 256 seconds (nominal).After a Reset, the default time-out period is 2 seconds.9.4 Clearing the WDTThe WDT is cleared when any of the following conditionsoccur:• Any Reset• CLRWDT instruction is executed• Device enters Sleep• Device wakes up from Sleep• Oscillator fail• WDT is disabledSee Table 9-2 for more information.9.5 Operation During SleepWhen the device enters Sleep, the WDT is cleared. Ifthe WDT is enabled during Sleep, the WDT resumescounting. When the device exits Sleep, the WDT iscleared again.When a WDT time-out occurs while the device is inSleep, no Reset is generated. Instead, the devicewakes up and resumes operation. The TO and PD bitsin the STATUS register are changed to indicate theevent. The RWDT bit in the PCON register can also beused. See Section 3.0 “Memory Organization” formore information.WDTE SWDTEN DeviceModeWDTMode11 X X ActiveAwake Active10 XSleep Disabled1Active01X0 Disabled00 X X DisabledTABLE 9-2: WDT CLEARING CONDITIONSConditionsWDTE = 00WDTE = 01 and SWDTEN = 0WDTE = 10 and enter SleepCLRWDT CommandOscillator Fail DetectedExit Sleep + System Clock = INTOSC, EXTCLKChange INTOSC divider (IRCF bits)WDTClearedUnaffectedDS41615A-page 80 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F15019.6 Watchdog Control RegisterREGISTER 9-1:WDTCON: WATCHDOG TIMER CONTROL REGISTERU-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0— — WDTPS SWDTENbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-6 Unimplemented: Read as ‘0’bit 5-1 WDTPS: Watchdog Timer Period Select bits (1)Bit Value = Prescale Rate00000 = 1:32 (Interval 1 ms nominal)00001 = 1:64 (Interval 2 ms nominal)00010 = 1:128 (Interval 4 ms nominal)00011 = 1:256 (Interval 8 ms nominal)00100 = 1:512 (Interval 16 ms nominal)00101 = 1:1024 (Interval 32 ms nominal)00110 = 1:2048 (Interval 64 ms nominal)00111 = 1:4096 (Interval 128 ms nominal)01000 = 1:8192 (Interval 256 ms nominal)01001 = 1:16384 (Interval 512 ms nominal)01010 = 1:32768 (Interval 1s nominal)01011 = 1:65536 (Interval 2s nominal) (Reset value)01100 = 1:131072 (2 17 ) (Interval 4s nominal)01101 = 1:262144 (2 18 ) (Interval 8s nominal)01110 = 1:524288 (2 19 ) (Interval 16s nominal)01111 = 1:1048576 (2 20 ) (Interval 32s nominal)10000 = 1:2097152 (2 21 ) (Interval 64s nominal)10001 = 1:4194304 (2 22 ) (Interval 128s nominal)10010 = 1:8388608 (2 23 ) (Interval 256s nominal)bit 0Note 1:10011 = Reserved. Results in minimum interval (1:32)•••11111 = Reserved. Results in minimum interval (1:32)SWDTEN: Software Enable/Disable for Watchdog Timer bitIf WDTE = 00:This bit is ignored.If WDTE = 01:1 = WDT is turned on0 = WDT is turned offIf WDTE = 1x:This bit is ignored.Times are approximate. WDT time is based on 31 kHz LFINTOSC. 2011 Microchip Technology Inc. Preliminary DS41615A-page 81

PIC12(L)F1501TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMERName Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Registeron PageOSCCON — IRCF — SCS 51PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 59STATUS — — — TO PD Z DC C 18WDTCON — — WDTPS SWDTEN 81Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.TABLE 9-4:SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMERName Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0Registeron PageCONFIG1Legend:13:8 — — — — CLKOUTEN BOREN —7:0 CP MCLRE PWRTE WDTE — FOSC— = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.40DS41615A-page 82 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150110.0 FLASH PROGRAM MEMORYCONTROLThe Flash program memory is readable and writableduring normal operation over the full VDD range.Program memory is indirectly addressed using SpecialFunction Registers (SFRs). The SFRs used to accessprogram memory are:• PMCON1• PMCON2• PMDATL• PMDATH• PMADRL• PMADRHWhen accessing the program memory, thePMDATH:PMDATL register pair forms a 2-byte wordthat holds the 14-bit data for read/write, and thePMADRH:PMADRL register pair forms a 2-byte wordthat holds the 15-bit address of the program memorylocation being read.The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip chargepump.The Flash program memory can be protected in twoways; by code protection (CP bit in Configuration Words)and write protection (WRT bits in ConfigurationWords).Code protection (CP = 0) (1) , disables access, readingand writing, to the Flash program memory via externaldevice programmers. Code protection does not affectthe self-write and erase functionality. Code protectioncan only be reset by a device programmer performinga Bulk Erase to the device, clearing all Flash programmemory, Configuration bits and User IDs.Write protection prohibits self-write and erase to aportion or all of the Flash program memory as definedby the bits WRT. Write protection does not affecta device programmers ability to read, write or erase thedevice.Note 1:Code protection of the entire Flashprogram memory array is enabled byclearing the CP bit of Configuration Words.10.1 PMADRL and PMADRH RegistersThe PMADRH:PMADRL register pair can address upto a maximum of 16K words of program memory. Whenselecting a program address value, the MSB of theaddress is written to the PMADRH register and the LSBis written to the PMADRL register.10.1.1 PMCON1 AND PMCON2REGISTERSPMCON1 is the control register for Flash programmemory accesses.Control bits RD and WR initiate read and write,respectively. These bits cannot be cleared, only set, insoftware. They are cleared by hardware at completionof the read or write operation. The inability to clear theWR bit in software prevents the accidental, prematuretermination of a write operation.The WREN bit, when set, will allow a write operation tooccur. On power-up, the WREN bit is clear. TheWRERR bit is set when a write operation is interruptedby a Reset during normal operation. In these situations,following Reset, the user can check the WRERR bitand execute the appropriate error handling routine.The PMCON2 register is a write-only register. Attemptingto read the PMCON2 register will return all ‘0’s.To enable writes to the program memory, a specificpattern (the unlock sequence), must be written to thePMCON2 register. The required unlock sequenceprevents inadvertent writes to the program memorywrite latches and Flash program memory.10.2 Flash Program Memory OverviewIt is important to understand the Flash program memorystructure for erase and programming operations. Flashprogram memory is arranged in rows. A row consists ofa fixed number of 14-bit program memory words. A rowis the minimum size that can be erased by user software.After a row has been erased, the user can reprogramall or a portion of this row. Data to be written into theprogram memory row is written to 14-bit wide data writelatches. These write latches are not directly accessibleto the user, but may be loaded via sequential writes tothe PMDATH:PMDATL register pair.Note:See Table 10-1 for Erase Row size and the number ofwrite latches for Flash program memory.TABLE 10-1:If the user wants to modify only a portionof a previously programmed row, then thecontents of the entire row must be readand saved in RAM prior to the erase.Then, new data and retained data can bewritten into the write latches to reprogramthe row of Flash program memory. However,any unprogrammed locations can bewritten without first erasing the row. In thiscase, it is not necessary to save andrewrite the other previously programmedlocations.DevicePIC12F1501PIC12LF1501FLASH MEMORYORGANIZATION BY DEVICERow Erase(words)WriteLatches(words)16 16 2011 Microchip Technology Inc. Preliminary DS41615A-page 83

PIC12(L)F150110.2.1 READING THE FLASH PROGRAMMEMORYTo read a program memory location, the user must:1. Write the desired address to thePMADRH:PMADRL register pair.2. Clear the CFGS bit of the PMCON1 register.3. Then, set control bit RD of the PMCON1 register.Once the read control bit is set, the program memoryFlash controller will use the second instruction cycle toread the data. This causes the second instructionimmediately following the “BSF PMCON1,RD” instructionto be ignored. The data is available in the very next cycle,in the PMDATH:PMDATL register pair; therefore, it canbe read as two bytes in the following instructions.PMDATH:PMDATL register pair will hold this value untilanother read or until it is written to by the user.Note:The two instructions following a programmemory read are required to be NOPs.This prevents the user from executing atwo-cycle instruction on the nextinstruction after the RD bit is set.FIGURE 10-1:FLASH PROGRAMMEMORY READFLOWCHARTStartRead OperationSelectProgram or Configuration Memory(CFGS)SelectWord Address(PMADRH:PMADRL)Initiate Read operation(RD = 1)Instruction Fetched ignoredNOP execution forcedInstruction Fetched ignoredNOP execution forcedData read now inPMDATH:PMDATLEndRead OperationDS41615A-page 84 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501FIGURE 10-2:FLASH PROGRAM MEMORY READ CYCLE EXECUTIONQ1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Flash ADDRPC PC + 1 PMADRH,PMADRL PC PC+3+ 3 PC + 4PC + 5Flash DataINSTR (PC) INSTR (PC + 1) PMDATH,PMDATL INSTR (PC + 3) INSTR (PC + 4)INSTR(PC - 1)executed hereBSF PMCON1,RDexecuted hereINSTR(PC + 1)instruction ignoredForced NOPexecuted hereINSTR(PC + 2)instruction ignoredForced NOPexecuted hereINSTR(PC + 3)executed hereINSTR(PC + 4)executed hereRD bitPMDATHPMDATLRegisterEXAMPLE 10-1:FLASH PROGRAM MEMORY READ* This code block will read 1 word of program* memory at the memory address:PROG_ADDR_HI: PROG_ADDR_LO* data will be returned in the variables;* PROG_DATA_HI, PROG_DATA_LOBANKSEL PMADRL ; Select Bank for PMCON registersMOVLW PROG_ADDR_LO ;MOVWF PMADRL ; Store LSB of addressMOVLW PROG_ADDR_HI ;MOVWF PMADRH ; Store MSB of addressBCF PMCON1,CFGS ; Do not select Configuration SpaceBSF PMCON1,RD ; Initiate readNOP ; Ignored (Figure 10-2)NOP ; Ignored (Figure 10-2)MOVF PMDATL,W ; Get LSB of wordMOVWF PROG_DATA_LO ; Store in user locationMOVF PMDATH,W ; Get MSB of wordMOVWF PROG_DATA_HI ; Store in user location 2011 Microchip Technology Inc. Preliminary DS41615A-page 85

PIC12(L)F150110.2.2 FLASH MEMORY UNLOCKSEQUENCEThe unlock sequence is a mechanism that protects theFlash program memory from unintended self-write programmingor erasing. The sequence must be executedand completed without interruption to successfullycomplete any of the following operations:• Row Erase• Load program memory write latches• Write of program memory write latches to programmemory• Write of program memory write latches to UserIDsThe unlock sequence consists of the following steps:1. Write 55h to PMCON22. Write AAh to PMCON23. Set the WR bit in PMCON14. NOP instruction5. NOP instructionOnce the WR bit is set, the processor will always forcetwo NOP instructions. When an Erase Row or ProgramRow operation is being performed, the processor will stallinternal operations (typical 2 ms), until the operation iscomplete and then resume with the next instruction.When the operation is loading the program memory writelatches, the processor will always force the two NOPinstructions and continue uninterrupted with the nextinstruction.Since the unlock sequence must not be interrupted,global interrupts should be disabled prior to the unlocksequence and re-enabled after the unlock sequence iscompleted.FIGURE 10-3:FLASH PROGRAMMEMORY UNLOCKSEQUENCE FLOWCHARTStartUnlock SequenceWrite 055h toPMCON2Write 0AAh toPMCON2InitiateWrite or Erase operation(WR = 1)Instruction Fetched ignoredNOP execution forcedInstruction Fetched ignoredNOP execution forcedEndUnlock SequenceDS41615A-page 86 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150110.2.3 ERASING FLASH PROGRAMMEMORYWhile executing code, program memory can only beerased by rows. To erase a row:1. Load the PMADRH:PMADRL register pair withany address within the row to be erased.2. Clear the CFGS bit of the PMCON1 register.3. Set the FREE and WREN bits of the PMCON1register.4. Write 55h, then AAh, to PMCON2 (Flashprogramming unlock sequence).5. Set control bit WR of the PMCON1 register tobegin the erase operation.See Example 10-2.After the “BSF PMCON1,WR” instruction, the processorrequires two cycles to set up the erase operation. Theuser must place two NOP instructions after the WR bit isset. The processor will halt internal operations for thetypical 2 ms erase time. This is not Sleep mode as theclocks and peripherals will continue to run. After theerase cycle, the processor will resume operation withthe third instruction after the PMCON1 write instruction.FIGURE 10-4:FLASH PROGRAMMEMORY ERASEFLOWCHARTStartErase OperationDisable Interrupts(GIE = 0)SelectProgram or Configuration Memory(CFGS)Select Row Address(PMADRH:PMADRL)Select Erase Operation(FREE = 1)Enable Write/Erase Operation(WREN = 1)Unlock Sequence(FIGURE Figure 10-3 x-x)CPU stalls whileErase operation completes(2ms typical)Disable Write/Erase Operation(WREN = 0)Re-enable Interrupts(GIE = 1)EndErase Operation 2011 Microchip Technology Inc. Preliminary DS41615A-page 87

PIC12(L)F1501EXAMPLE 10-2:ERASING ONE ROW OF PROGRAM MEMORY; This row erase routine assumes the following:; 1. A valid address within the erase row is loaded in ADDRH:ADDRL; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)BCF INTCON,GIE ; Disable ints so required sequences will execute properlyBANKSEL PMADRLMOVF ADDRL,W ; Load lower 8 bits of erase address boundaryMOVWF PMADRLMOVF ADDRH,W ; Load upper 6 bits of erase address boundaryMOVWF PMADRHBCF PMCON1,CFGS ; Not configuration spaceBSF PMCON1,FREE ; Specify an erase operationBSF PMCON1,WREN ; Enable writesRequiredSequenceMOVLW 55h ; Start of required sequence to initiate eraseMOVWF PMCON2 ; Write 55hMOVLW 0AAh ;MOVWF PMCON2 ; Write AAhBSF PMCON1,WR ; Set WR bit to begin eraseNOP; NOP instructions are forced as processor startsNOP; row erase of program memory.;; The processor stalls until the erase process is complete; after erase processor continues with 3rd instructionBCF PMCON1,WREN ; Disable writesBSF INTCON,GIE ; Enable interruptsDS41615A-page 88 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150110.2.4 WRITING TO FLASH PROGRAMMEMORYProgram memory is programmed using the followingsteps:1. Load the address in PMADRH:PMADRL of therow to be programmed.2. Load each write latch with data.3. Initiate a programming operation.4. Repeat steps 1 through 3 until all data is written.Before writing to program memory, the word(s) to bewritten must be erased or previously unwritten. Programmemory can only be erased one row at a time. Noautomatic erase occurs upon the initiation of the write.Program memory can be written one or more words ata time. The maximum number of words written at onetime is equal to the number of write latches. SeeFigure 10-5 (row writes to program memory with 16write latches) for more details.The write latches are aligned to the Flash row addressboundary defined by the upper 11-bits ofPMADRH:PMADRL, (PMADRH:PMADRL)with the lower 4-bits of PMADRL, (PMADRL)determining the write latch being loaded. Write operationsdo not cross these boundaries. At the completionof a program memory write operation, the data in thewrite latches is reset to contain 0x3FFF.The following steps should be completed to load thewrite latches and program a row of program memory.These steps are divided into two parts. First, each writelatch is loaded with data from the PMDATH:PMDATLusing the unlock sequence with LWLO = 1. When thelast word to be loaded into the write latch is ready, theLWLO bit is cleared and the unlock sequenceexecuted. This initiates the programming operation,writing all the latches into Flash program memory.Note:The special unlock sequence is requiredto load a write latch with data or initiate aFlash programming operation. If theunlock sequence is interrupted, writing tothe latches or program memory will not beinitiated.1. Set the WREN bit of the PMCON1 register.2. Clear the CFGS bit of the PMCON1 register.3. Set the LWLO bit of the PMCON1 register.When the LWLO bit of the PMCON1 register is‘1’, the write sequence will only load the writelatches and will not initiate the write to Flashprogram memory.4. Load the PMADRH:PMADRL register pair withthe address of the location to be written.5. Load the PMDATH:PMDATL register pair withthe program memory data to be written.6. Execute the unlock sequence (Section 10.2.2“Flash Memory Unlock Sequence”). The writelatch is now loaded.7. Increment the PMADRH:PMADRL register pairto point to the next location.8. Repeat steps 5 through 7 until all but the lastwrite latch has been loaded.9. Clear the LWLO bit of the PMCON1 register.When the LWLO bit of the PMCON1 register is‘0’, the write sequence will initiate the write toFlash program memory.10. Load the PMDATH:PMDATL register pair withthe program memory data to be written.11. Execute the unlock sequence (Section 10.2.2“Flash Memory Unlock Sequence”). Theentire program memory latch content is nowwritten to Flash program memory.Note: The program memory write latches arereset to the blank state (0x3FFF) at thecompletion of every write or eraseoperation. As a result, it is not necessaryto load all the program memory writelatches. Unloaded latches will remain inthe blank state.An example of the complete write sequence is shown inExample 10-3. The initial address is loaded into thePMADRH:PMADRL register pair; the data is loadedusing indirect addressing. 2011 Microchip Technology Inc. Preliminary DS41615A-page 89

PIC12(L)F1501FIGURE 10-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 16 WRITE LATCHES7 6 0 7 5 4 07 5 0 7 0PMADRH PMADRL- r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 c3 c2 c1 c0- -PMDATH PMDATL6 814Program Memory Write Latches11414141414PMADRLWrite Latch #000hWrite Latch #101hWrite Latch #140EhWrite Latch #150Fh14 14 14 14RowAddrAddr AddrAddr000h 0000h 0001h000Eh001Fh001h 0010h 0011h001Eh001FhCFGS = 0002h 0020h 0021h002Eh002Fh7FEh 7FE0h 7FE1h7FEEh7FEFhPMADRH:PMADRLRowAddressDecode7FFh 7FF0h 7FF1h7FFEh7FFFhFlash Program Memory800h 8000h - 8003h 8004h - 8005h 8006h 8007h – 8008h8009h - 801FhCFGS = 1USER ID 0 - 3reservedDEVICEIDREVIDConfigurationWordsreservedConfiguration MemoryDS41615A-page 90 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501FIGURE 10-6:FLASH PROGRAM MEMORY WRITE FLOWCHARTStartWrite OperationDetermine number of wordsto be written into Program orConfiguration Memory.The number of words cannotexceed the number of wordsper row.(word_cnt)Enable Write/EraseOperation (WREN = 1)Load the value to write(PMDATH:PMDATL)Disable Interrupts(GIE = 0)Update the word counter(word_cnt--)Write Latches to Flash(LWLO = 0)SelectProgram or Config. Memory(CFGS)Last word towrite ?Unlock SequenceYes (Figure 10-3 x-x)Select Row Address(PMADRH:PMADRL)NoUnlock Sequence(Figure 10-3 x-x)CPU stalls while Writeoperation completes(2ms typical)Select Write Operation(FREE = 0)Load Write Latches Only(LWLO = 1)No delay when writing toProgram Memory LatchesIncrement Address(PMADRH:PMADRL++)DisableWrite/Erase Operation(WREN = 0)Re-enable Interrupts(GIE = 1)EndWrite Operation 2011 Microchip Technology Inc. Preliminary DS41615A-page 91

PIC12(L)F1501EXAMPLE 10-3:WRITING TO FLASH PROGRAM MEMORY; This write routine assumes the following:; 1. 32 bytes of data are loaded, starting at the address in DATA_ADDR; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,; stored in little endian format; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM);BCF INTCON,GIE ; Disable ints so required sequences will execute properlyBANKSEL PMADRH ; Bank 3MOVF ADDRH,W ; Load initial addressMOVWF PMADRH ;MOVF ADDRL,W ;MOVWF PMADRL ;MOVLW LOW DATA_ADDR ; Load initial data addressMOVWF FSR0L ;MOVLW HIGH DATA_ADDR ; Load initial data addressMOVWF FSR0H ;BCF PMCON1,CFGS ; Not configuration spaceBSF PMCON1,WREN ; Enable writesBSF PMCON1,LWLO ; Only Load Write LatchesLOOPMOVIW FSR0++ ; Load first data byte into lowerMOVWF PMDATL ;MOVIW FSR0++ ; Load second data byte into upperMOVWF PMDATH ;MOVF PMADRL,W ; Check if lower bits of address are '00000'XORLW 0x0F ; Check if we're on the last of 16 addressesANDLW 0x0F ;BTFSC STATUS,Z ; Exit if last of 16 words,GOTO START_WRITE ;RequiredSequenceMOVLW 55h ; Start of required write sequence:MOVWF PMCON2 ; Write 55hMOVLW 0AAh ;MOVWF PMCON2 ; Write AAhBSF PMCON1,WR ; Set WR bit to begin writeNOP; NOP instructions are forced as processor; loads program memory write latchesNOP ;INCF PMADRL,F ; Still loading latches Increment addressGOTO LOOP ; Write next latchesSTART_WRITEBCF PMCON1,LWLO ; No more loading latches - Actually start Flash program; memory writeRequiredSequenceMOVLW 55h ; Start of required write sequence:MOVWF PMCON2 ; Write 55hMOVLW 0AAh ;MOVWF PMCON2 ; Write AAhBSF PMCON1,WR ; Set WR bit to begin writeNOP; NOP instructions are forced as processor writes; all the program memory write latches simultaneouslyNOP; to program memory.; After NOPs, the processor; stalls until the self-write process in complete; after write processor continues with 3rd instructionBCF PMCON1,WREN ; Disable writesBSF INTCON,GIE ; Enable interruptsDS41615A-page 92 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150110.3 Modifying Flash Program MemoryWhen modifying existing data in a program memoryrow, and data within that row must be preserved, it mustfirst be read and saved in a RAM image. Programmemory is modified using the following steps:1. Load the starting address of the row to bemodified.2. Read the existing data from the row into a RAMimage.3. Modify the RAM image to contain the new datato be written into program memory.4. Load the starting address of the row to berewritten.5. Erase the program memory row.6. Load the write latches with data from the RAMimage.7. Initiate a programming operation.FIGURE 10-7:FLASH PROGRAMMEMORY MODIFYFLOWCHARTStartModify OperationRead Operation(Figure 10-2 x.x)An image of the entire row readmust be stored in RAMModify ImageThe words to be modified arechanged in the RAM imageErase Operation(Figure 10-4 x.x)Write Operationuse RAM image(Figure 10-5 x.x)EndModify Operation 2011 Microchip Technology Inc. Preliminary DS41615A-page 93

PIC12(L)F150110.4 User ID, Device ID andConfiguration Word AccessInstead of accessing program memory, the User ID’s,Device ID/Revision ID and Configuration Words can beaccessed when CFGS = 1 in the PMCON1 register.This is the region that would be pointed to byPC = 1, but not all addresses are accessible.Different access may exist for reads and writes. Referto Table 10-2.When read access is initiated on an address outsidethe parameters listed in Table 10-2, thePMDATH:PMDATL register pair is cleared, readingback ‘0’s.TABLE 10-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)Address Function Read Access Write Access8000h-8003h User IDs Yes Yes8006h Device ID/Revision ID Yes No8007h-8008h Configuration Words 1 and 2 Yes NoEXAMPLE 10-4: CONFIGURATION WORD AND DEVICE ID ACCESS* This code block will read 1 word of program memory at the memory address:* PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;* PROG_DATA_HI, PROG_DATA_LOBANKSEL PMADRL ; Select correct BankMOVLW PROG_ADDR_LO ;MOVWF PMADRL ; Store LSB of addressCLRF PMADRH ; Clear MSB of addressBSF PMCON1,CFGS ; Select Configuration SpaceBCF INTCON,GIE ; Disable interruptsBSF PMCON1,RD ; Initiate readNOP ; Executed (See Figure 10-2)NOP ; Ignored (See Figure 10-2)BSF INTCON,GIE ; Restore interruptsMOVF PMDATL,W ; Get LSB of wordMOVWF PROG_DATA_LO ; Store in user locationMOVF PMDATH,W ; Get MSB of wordMOVWF PROG_DATA_HI ; Store in user locationDS41615A-page 94 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150110.5 Write VerifyIt is considered good programming practice to verify thatprogram memory writes agree with the intended value.Since program memory is stored as a full page then thestored program memory contents are compared with theintended data stored in RAM after the last write iscomplete.FIGURE 10-8:FLASH PROGRAMMEMORY VERIFYFLOWCHARTStartVerify OperationThis routine assumes that the last rowof data written was from an imagesaved in RAM. This image will be usedto verify the data currently stored inFlash Program Memory.Read Operation(Figure 10-2 x.x)PMDAT =RAM image?YesNoFailVerify OperationNoLastWord ?YesEndVerify Operation 2011 Microchip Technology Inc. Preliminary DS41615A-page 95

PIC12(L)F150110.6 Flash Program Memory Control RegistersREGISTER 10-1:PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTERR/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/uPMDATbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-0PMDAT: Read/write value for Least Significant bits of program memoryREGISTER 10-2:PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTERU-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u— — PMDATbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-6 Unimplemented: Read as ‘0’bit 5-0PMDAT: Read/write value for Most Significant bits of program memoryREGISTER 10-3: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTERR/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0PMADRbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-0PMADR: Specifies the Least Significant bits for program memory addressREGISTER 10-4:PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTERU-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0— PMADRbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7 Unimplemented: Read as ‘1’bit 6-0PMADR: Specifies the Most Significant bits for program memory addressDS41615A-page 96 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501REGISTER 10-5:PMCON1: PROGRAM MEMORY CONTROL 1 REGISTERU-1 (1) R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q (2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0— CFGS LWLO FREE WRERR WREN WR RDbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardwarebit 7 Unimplemented: Read as ‘1’bit 6CFGS: Configuration Select bit1 = Access Configuration, User ID and Device ID Registers0 = Access Flash program memorybit 5 LWLO: Load Write Latches Only bit (3)1 = Only the addressed program memory write latch is loaded/updated on the next WR command0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latcheswill be initiated on the next WR commandbit 4FREE: Program Flash Erase Enable bit1 = Performs an erase operation on the next WR command (hardware cleared upon completion)0 = Performs an write operation on the next WR commandbit 3WRERR: Program/Erase Error Flag bit1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automaticallyon any set attempt (write ‘1’) of the WR bit).0 = The program or erase operation completed normallybit 2WREN: Program/Erase Enable bit1 = Allows program/erase cycles0 = Inhibits programming/erasing of program Flashbit 1WR: Write Control bit1 = Initiates a program Flash program/erase operation.The operation is self-timed and the bit is cleared by hardware once operation is complete.The WR bit can only be set (not cleared) in software.0 = Program/erase operation to the Flash is complete and inactivebit 0RD: Read Control bit1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set(not cleared) in software.0 = Does not initiate a program Flash readNote 1: Unimplemented bit, read as ‘1’.2: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1).3: The LWLO bit is ignored during a program memory erase operation (FREE = 1). 2011 Microchip Technology Inc. Preliminary DS41615A-page 97

PIC12(L)F1501REGISTER 10-6:PMCON2: PROGRAM MEMORY CONTROL 2 REGISTERW-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0Program Memory Control Register 2bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-0Flash Memory Unlock Pattern bitsTo unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of thePMCON1 register. The value written to this register is used to unlock the writes. There are specifictiming requirements on these writes.TABLE 10-3:SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORYName Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Register onPagePMCON1 — CFGS LWLO FREE WRERR WREN WR RD 97PMCON2 Program Memory Control Register 2 98PMADRL PMADRL 96PMADRH — PMADRH 96PMDATL PMDATL 96PMDATH — — PMDATH 96INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66Legend:TABLE 10-4:— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory module.SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORYName Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0Registeron PageCONFIG1CONFIG2Legend:13:8 — — — — CLKOUTEN BOREN —7:0 CP MCLRE PWRTE WDTE — FOSC13:8 — — LVP — LPBOR BORV STVREN —7:0 — — — — — — WRT— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.4041DS41615A-page 98 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150111.0 I/O PORTSEach port has three standard registers for its operation.These registers are:• TRISx registers (data direction)• PORTx registers (reads the levels on the pins ofthe device)• LATx registers (output latch)Some ports may have one or more of the followingadditional registers. These registers are:• ANSELx (analog select)• WPUx (weak pull-up)In general, when a peripheral is enabled on a port pin,that pin cannot be used as a general purpose output.However, the pin can still be read.TABLE 11-1:DevicePIC12(L)F1501PORT AVAILABILITY PERDEVICEPORTAThe Data Latch (LATx registers) is useful forread-modify-write operations on the value that the I/Opins are driving.A write operation to the LATx register has the sameeffect as a write to the corresponding PORTx register.A read of the LATx register reads of the values held inthe I/O PORT latches, while a read of the PORTxregister reads the actual I/O pin value.Ports that support analog inputs have an associatedANSELx register. When an ANSEL bit is set, the digitalinput buffer associated with that bit is disabled.Disabling the input buffer prevents analog signal levelson the pin between a logic high and low from causingexcessive current in the logic input circuitry. Asimplified model of a generic I/O port, without theinterfaces to other peripherals, is shown in Figure 11-1.●FIGURE 11-1:Write LATxWrite PORTxData BusRead PORTxTo peripheralsDEXAMPLE 11-1:CKGENERIC I/O PORTOPERATIONRead LATxQData RegisterANSELxTRISxVDDVSSINITIALIZING PORTAI/O pin; This code example illustrates; initializing the PORTA register. The; other ports are initialized in the same; manner.BANKSEL PORTA ;CLRF PORTA ;Init PORTABANKSEL LATA ;Data LatchCLRF LATA ;BANKSEL ANSELA ;CLRF ANSELA ;digital I/OBANKSEL TRISA ;MOVLW B'00111000' ;Set RA as inputsMOVWF TRISA ;and set RA as;outputs 2011 Microchip Technology Inc. Preliminary DS41615A-page 99

PIC12(L)F150111.1 Alternate Pin FunctionThe Alternate Pin Function Control (APFCON) registeris used to steer specific peripheral input and outputfunctions between different pins. The APFCON registeris shown in Register 11-1. For this device family, thefollowing functions can be moved between differentpins.• SDO• SS• T1G• CLC1• NCO1These bits have no effect on the values of any TRISregister. PORT and TRIS overrides will be routed to thecorrect pin. The unselected pin will be unaffected.REGISTER 11-1:APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTERR/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 U-0 R/W-0/0 R/W-0/0CWG1BSEL CWG1ASEL — — T1GSEL — CLC1SEL NCO1SELbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7CWG1BSEL: Pin Selection bit1 = CWG1B function is on RA40 = CWG1B function is on RA0bit 6CWG1ASEL: Pin Selection bit1 = CWG1A function is on RA50 = CWG1A function is on RA2bit 5-4 Unimplemented: Read as ‘0’bit 3T1GSEL: Pin Selection bit1 = T1G function is on RA30 = T1G function is on RA4bit 2 Unimplemented: Read as ‘0’bit 1bit 0CLC1SEL: Pin Selection bit1 = CLC1 function is on RA40 = CLC1 function is on RA2NCO1SEL: Pin Selection bit1 = NCO1 function is on RA50 = NCO1 function is on RA1DS41615A-page 100 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150111.2 PORTA RegistersPORTA is a 6-bit wide, bidirectional port. Thecorresponding data direction register is TRISA(Register 11-3). Setting a TRISA bit (= 1) will make thecorresponding PORTA pin an input (i.e., disable theoutput driver). Clearing a TRISA bit (= 0) will make thecorresponding PORTA pin an output (i.e., enablesoutput driver and puts the contents of the output latchon the selected pin). The exception is RA3, which isinput only and its TRIS bit will always read as ‘1’.Example 11-1 shows how to initialize an I/O port.Reading the PORTA register (Register 11-2) reads thestatus of the pins, whereas writing to it will write to thePORT latch. All write operations are read-modify-writeoperations. Therefore, a write to a port implies that theport pins are read, this value is modified and thenwritten to the PORT data latch (LATA).The TRISA register (Register 11-3) controls thePORTA pin output drivers, even when they are beingused as analog inputs. The user should ensure the bitsin the TRISA register are maintained set when usingthem as analog inputs. I/O pins configured as analoginput always read ‘0’.11.2.1 ANSELA REGISTERThe ANSELA register (Register 11-5) is used toconfigure the Input mode of an I/O pin to analog.Setting the appropriate ANSELA bit high will cause alldigital reads on the pin to be read as ‘0’ and allowanalog functions on the pin to operate correctly.The state of the ANSELA bits has no effect on digitaloutput functions. A pin with TRIS clear and ANSEL setwill still operate as a digital output, but the Input modewill be analog. This can cause unexpected behaviorwhen executing read-modify-write instructions on theaffected port.Note:The ANSELA bits default to the Analogmode after Reset. To use any pins asdigital general purpose or peripheralinputs, the corresponding ANSEL bitsmust be initialized to ‘0’ by user software.11.2.2 PORTA FUNCTIONS AND OUTPUTPRIORITIESEach PORTA pin is multiplexed with other functions. Thepins, their combined functions and their output prioritiesare shown in Table 11-2.When multiple outputs are enabled, the actual pincontrol goes to the peripheral with the highest priority.Analog input functions, such as ADC and comparatorinputs, are not shown in the priority lists. These inputsare active when the I/O pin is set for Analog mode usingthe ANSELx registers. Digital output functions maycontrol the pin when it is in Analog mode with thepriority shown in Table 11-2.TABLE 11-2:PORTA OUTPUT PRIORITYPin Name Function Priority (1)RA0ICSPDATDACOUT1CWG1B (2)PWM2RA0RA1 NCO1 (2)RA1RA2DACOUT2CWG1A (2)CWG1FLTCLC1 (2)C1OUTPWM1RA2RA3NoneRA4CLKOUTCWG1B (3)CLC1 (3)PWM3RA4RA5 CWG1A (3)CLC2NCO1 (3)PWM4RA5Note 1: Priority listed from highest to lowest.2: Default pin (see APFCON register).3: Alternate pin (see APFCON register). 2011 Microchip Technology Inc. Preliminary DS41615A-page 101

PIC12(L)F1501REGISTER 11-2:PORTA: PORTA REGISTERU-0 U-0 R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x— — RA5 RA4 RA3 RA2 RA1 RA0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-6 Unimplemented: Read as ‘0’bit 5-0 RA: PORTA I/O Value bits (1)1 = Port pin is > VIH0 = Port pin is < VILNote 1:Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is returnof actual I/O pin values.REGISTER 11-3:TRISA: PORTA TRI-STATE REGISTERU-0 U-0 R/W-1/1 R/W-1/1 U-1 R/W-1/1 R/W-1/1 R/W-1/1— — TRISA5 TRISA4 — (1) TRISA2 TRISA1 TRISA0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-6 Unimplemented: Read as ‘0’bit 5-4 TRISA: PORTA Tri-State Control bit1 = PORTA pin configured as an input (tri-stated)0 = PORTA pin configured as an outputbit 3 Unimplemented: Read as ‘1’bit 2-0 TRISA: PORTA Tri-State Control bit1 = PORTA pin configured as an input (tri-stated)0 = PORTA pin configured as an outputNote 1: Unimplemented, read as ‘1’.DS41615A-page 102 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501REGISTER 11-4:LATA: PORTA DATA LATCH REGISTERU-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u— — LATA5 LATA4 — LATA2 LATA1 LATA0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-6 Unimplemented: Read as ‘0’bit 5-4 LATA: RA Output Latch Value bits (1)bit 3 Unimplemented: Read as ‘0’bit 2-0 LATA: RA Output Latch Value bits (1)Note 1:Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is returnof actual I/O pin values.REGISTER 11-5:ANSELA: PORTA ANALOG SELECT REGISTERU-0 U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1— — — ANSA4 — ANSA2 ANSA1 ANSA0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-5 Unimplemented: Read as ‘0’bit 4 ANSA4: Analog Select between Analog or Digital Function on pins RA4, respectively1 = Analog input. Pin is assigned as analog input (1) . Digital input buffer disabled.0 = Digital I/O. Pin is assigned to port or digital special function.bit 3 Unimplemented: Read as ‘0’bit 2-0 ANSA: Analog Select between Analog or Digital Function on pins RA, respectively1 = Analog input. Pin is assigned as analog input (1) . Digital input buffer disabled.0 = Digital I/O. Pin is assigned to port or digital special function.Note 1:When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order toallow external control of the voltage on the pin. 2011 Microchip Technology Inc. Preliminary DS41615A-page 103

PIC12(L)F1501REGISTER 11-6:WPUA: WEAK PULL-UP PORTA REGISTERU-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1— — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-6 Unimplemented: Read as ‘0’bit 5-0 WPUA: Weak Pull-up Register bits (3)1 = Pull-up enabled0 = Pull-up disabledNote 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.2: The weak pull-up device is automatically disabled if the pin is in configured as an output.3: For the WPUA3 bit, when MCLRE = 1, weak pull-up is internally enabled, but not reported here.TABLE 11-3:SUMMARY OF REGISTERS ASSOCIATED WITH PORTAName Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Registeron PageANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 103APFCON CWG1BSEL CWG1ASEL — — T1GSEL — CLC1SEL NCO1SEL 100LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 103OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS 143PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 102TRISA — — TRISA5 TRISA4 — (1) TRISA2 TRISA1 TRISA0 102WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 104Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.Note 1: Unimplemented, read as ‘1’.TABLE 11-4:SUMMARY OF CONFIGURATION WORD WITH PORTAName Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0Registeron PageCONFIG1Legend:13:8 — — — — CLKOUTEN BOREN —7:0 CP MCLRE PWRTE WDTE — FOSC— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.40DS41615A-page 104 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150112.0 INTERRUPT-ON-CHANGEThe PORTA and PORTB pins can be configured tooperate as Interrupt-On-Change (IOC) pins. An interruptcan be generated by detecting a signal that has either arising edge or a falling edge. Any individual port pin, orcombination of port pins, can be configured to generatean interrupt. The interrupt-on-change module has thefollowing features:• Interrupt-on-Change enable (Master Switch)• Individual pin configuration• Rising and falling edge detection• Individual pin interrupt flagsFigure 12-1 is a block diagram of the IOC module.12.1 Enabling the ModuleTo allow individual port pins to generate an interrupt, theIOCIE bit of the INTCON register must be set. If theIOCIE bit is disabled, the edge detection on the pin willstill occur, but an interrupt will not be generated.12.2 Individual Pin ConfigurationFor each port pin, a rising edge detector and a fallingedge detector are present. To enable a pin to detect arising edge, the associated bit of the IOCxP register isset. To enable a pin to detect a falling edge, theassociated bit of the IOCxN register is set.A pin can be configured to detect rising and fallingedges simultaneously by setting both associated bits ofthe IOCxP and IOCxN registers, respectively.12.3 Interrupt FlagsThe IOCAFx and IOCBFx bits located in the IOCAF andIOCBF registers, respectively, are status flags thatcorrespond to the interrupt-on-change pins of theassociated port. If an expected edge is detected on anappropriately enabled pin, then the status flag for that pinwill be set, and an interrupt will be generated if the IOCIEbit is set. The IOCIF bit of the INTCON register reflectsthe status of all IOCAFx and IOCBFx bits.12.4 Clearing Interrupt FlagsThe individual status flags, (IOCAFx and IOCBFx bits),can be cleared by resetting them to zero. If another edgeis detected during this clearing operation, the associatedstatus flag will be set at the end of the sequence,regardless of the value actually being written.In order to ensure that no detected edge is lost whileclearing flags, only AND operations masking out knownchanged bits should be performed. The followingsequence is an example of what should be performed.EXAMPLE 12-1:MOVLWXORWFANDWF0xffIOCAF, WIOCAF, F12.5 Operation in SleepCLEARING INTERRUPTFLAGS(PORTA EXAMPLE)The interrupt-on-change interrupt sequence will wakethe device from Sleep mode, if the IOCIE bit is set.If an edge is detected while in Sleep mode, the IOCxFregister will be updated prior to the first instructionexecuted out of Sleep. 2011 Microchip Technology Inc. Preliminary DS41615A-page 105

PIC12(L)F1501FIGURE 12-1:INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE)IOCANxDQQ4Q1CKREdgeDetectRAxIOCAPxDQData Bus =0 or 1DSQTo Data BusIOCAFxCKRWrite IOCAFxCKIOCIEQ2From all otherIOCAFx individualpin detectorsIOC interruptto CPU coreQ1Q2Q3Q4Q4Q1Q1Q1Q2Q2Q3Q3Q4Q4Q4Q4Q1 Q4Q1 Q4Q1DS41615A-page 106 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150112.6 Interrupt-On-Change RegistersREGISTER 12-1:IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTERU-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0— — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-6 Unimplemented: Read as ‘0’bit 5-0IOCAP: Interrupt-on-Change PORTA Positive Edge Enable bits1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will be setupon detecting an edge.0 = Interrupt-on-Change disabled for the associated pin.REGISTER 12-2:IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTERU-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0— — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-6 Unimplemented: Read as ‘0’bit 5-0IOCAN: Interrupt-on-Change PORTA Negative Edge Enable bits1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will be setupon detecting an edge.0 = Interrupt-on-Change disabled for the associated pin.REGISTER 12-3:IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTERU-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0— — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardwarebit 7-6 Unimplemented: Read as ‘0’bit 5-0IOCAF: Interrupt-on-Change PORTA Flag bits1 = An enabled change was detected on the associated pin.Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge wasdetected on RAx.0 = No change was detected, or the user cleared the detected change 2011 Microchip Technology Inc. Preliminary DS41615A-page 107

PIC12(L)F1501TABLE 12-1:SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGEName Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Registeron PageANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 103INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 107IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 107IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 107TRISA — — TRISA5 TRISA4—(1)TRISA2 TRISA1 TRISA0 102Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.Note 1: Unimplemented, read as ‘1’.DS41615A-page 108 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150113.0 FIXED VOLTAGE REFERENCE(FVR)The Fixed Voltage Reference, or FVR, is a stablevoltage reference, independent of VDD, with 1.024V,2.048V or 4.096V selectable output levels. The outputof the FVR can be configured to supply a referencevoltage to the following:• ADC input channel• Comparator positive input• Comparator negative inputThe FVR can be enabled by setting the FVREN bit ofthe FVRCON register.13.1 Independent Gain AmplifierThe output of the FVR supplied to the ADC andcomparators is routed through a programmable gainamplifier. Each amplifier can be programmed for a gainof 1x, 2x or 4x, to produce the three possible voltagelevels.The ADFVR bits of the FVRCON register areused to enable and configure the gain amplifier settingsfor the reference supplied to the ADC module. ReferenceSection 15.0 “Analog-to-Digital Converter(ADC) Module” for additional information.The CDAFVR bits of the FVRCON register areused to enable and configure the gain amplifier settingsfor the reference supplied to the comparator modules.Reference Section 17.0 “Comparator Module” foradditional information.13.2 FVR Stabilization PeriodWhen the Fixed Voltage Reference module is enabled, itrequires time for the reference and amplifier circuits tostabilize. Once the circuits stabilize and are ready for use,the FVRRDY bit of the FVRCON register will be set. SeeSection 27.0 “Electrical Specifications” for theminimum delay requirement.FIGURE 13-1:VOLTAGE REFERENCE BLOCK DIAGRAMADFVR2X1X2X4FVR BUFFER1(To ADC Module)CDAFVR2X1X2X4FVR BUFFER2(To Comparators)FVRENAny peripheral requiring theFixed Reference(See Table 13-1)+_FVRRDYTABLE 13-1:PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)Peripheral Conditions DescriptionHFINTOSCBORLDOFOSC = 00 andIRCF = 000xBOREN = 11BOREN = 10 and BORFS = 1BOREN = 01 and BORFS = 1All PIC12F1501 devices, whenVREGPM = 1 and not in SleepINTOSC is active and device is not in Sleep.BOR always enabled.BOR disabled in Sleep mode, BOR Fast Start enabled.BOR under software control, BOR Fast Start enabled.The device runs off of the Low-Power Regulator when inSleep mode. 2011 Microchip Technology Inc. Preliminary DS41615A-page 109

PIC12(L)F150113.3 FVR Control RegistersREGISTER 13-1:FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTERR/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0FVREN FVRRDY (1) TSEN TSRNG CDAFVR ADFVRbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on conditionbit 7FVREN: Fixed Voltage Reference Enable bit1 = Fixed Voltage Reference is enabled0 = Fixed Voltage Reference is disabledbit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit (1)1 = Fixed Voltage Reference output is ready for use0 = Fixed Voltage Reference output is not ready or not enabledbit 5 TSEN: Temperature Indicator Enable bit (3)1 = Temperature Indicator is enabled0 = Temperature Indicator is disabledbit 4 TSRNG: Temperature Indicator Range Selection bit (3)1 = VOUT = VDD - 4VT (High Range)0 = VOUT = VDD - 2VT (Low Range)bit 3-2 CDAFVR: Comparator Fixed Voltage Reference Selection bits11 = Comparator Fixed Voltage Reference Peripheral output is 4x (4.096V) (2)10 = Comparator Fixed Voltage Reference Peripheral output is 2x (2.048V) (2)01 = Comparator Fixed Voltage Reference Peripheral output is 1x (1.024V)00 = Comparator Fixed Voltage Reference Peripheral output is offbit 1-0 ADFVR: ADC Fixed Voltage Reference Selection bit11 = ADC Fixed Voltage Reference Peripheral output is 4x (4.096V) (2)10 = ADC Fixed Voltage Reference Peripheral output is 2x (2.048V) (2)01 = ADC Fixed Voltage Reference Peripheral output is 1x (1.024V)00 = ADC Fixed Voltage Reference Peripheral output is offNote 1: FVRRDY is always ‘1’ for the PIC12F1501 devices.2: Fixed Voltage Reference output cannot exceed VDD.3: See Section 14.0 “Temperature Indicator Module” for additional information.TABLE 13-2:SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCEName Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Registeron pageFVRCON FVREN FVRRDY TSEN TSRNG CDAFVR>1:0> ADFVR 110Legend:Shaded cells are unused by the Fixed Voltage Reference module.DS41615A-page 110 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150114.0 TEMPERATURE INDICATORMODULEFIGURE 14-1:TEMPERATURE CIRCUITDIAGRAMThis family of devices is equipped with a temperaturecircuit designed to measure the operating temperatureof the silicon die. The circuit’s range of operatingtemperature falls between -40°C and +85°C. Theoutput is a voltage that is proportional to the devicetemperature. The output of the temperature indicator isinternally connected to the device ADC.The circuit may be used as a temperature thresholddetector or a more accurate temperature indicator,depending on the level of calibration performed. A onepointcalibration allows the circuit to indicate atemperature closely surrounding that point. A two-pointcalibration allows the circuit to sense the entire rangeof temperature more accurately. Reference ApplicationNote AN1333, “Use and Calibration of the InternalTemperature Indicator” (DS01333) for more detailsregarding the calibration process.VDDTSENTSRNGVOUTTo ADC14.1 Circuit OperationFigure 14-1 shows a simplified block diagram of thetemperature circuit. The proportional voltage output isachieved by measuring the forward voltage drop acrossmultiple silicon junctions.Equation 14-1 describes the output characteristics ofthe temperature indicator.EQUATION 14-1:VOUT RANGESHigh Range: VOUT = VDD - 4VTLow Range: VOUT = VDD - 2VTThe temperature sense circuit is integrated with theFixed Voltage Reference (FVR) module. SeeSection 13.0 “Fixed Voltage Reference (FVR)” formore information.The circuit is enabled by setting the TSEN bit of theFVRCON register. When disabled, the circuit draws nocurrent.The circuit operates in either high or low range. The highrange, selected by setting the TSRNG bit of theFVRCON register, provides a wider output voltage. Thisprovides more resolution over the temperature range,but may be less consistent from part to part. This rangerequires a higher bias voltage to operate and thus, ahigher VDD is needed.The low range is selected by clearing the TSRNG bit ofthe FVRCON register. The low range generates a lowervoltage drop and thus, a lower bias voltage is needed tooperate the circuit. The low range is provided for lowvoltage operation.14.2 Minimum Operating VDDWhen the temperature circuit is operated in low range,the device may be operated at any operating voltagethat is within specifications.When the temperature circuit is operated in high range,the device operating voltage, VDD, must be highenough to ensure that the temperature circuit is correctlybiased.Table 14-1 shows the recommended minimum VDD vs.range setting.TABLE 14-1:RECOMMENDED VDD VS.RANGEMin. VDD, TSRNG = 1 Min. VDD, TSRNG = 03.6V 1.8V14.3 Temperature OutputThe output of the circuit is measured using the internalAnalog-to-Digital Converter. A channel is reserved forthe temperature circuit output. Refer to Section 15.0“Analog-to-Digital Converter (ADC) Module” fordetailed information.14.4 ADC Acquisition TimeTo ensure accurate temperature measurements, theuser must wait at least 200 s after the ADC inputmultiplexer is connected to the temperature indicatoroutput before the conversion is performed. In addition,the user must wait 200 s between sequentialconversions of the temperature indicator output. 2011 Microchip Technology Inc. Preliminary DS41615A-page 111

PIC12(L)F1501TABLE 14-2:SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATORName Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Registeron pageFVRCON FVREN FVRRDY TSEN TSRNG CDAFVR ADFVR 118Legend:Shaded cells are unused by the temperature indicator module.DS41615A-page 112 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150115.0 ANALOG-TO-DIGITALCONVERTER (ADC) MODULEThe Analog-to-Digital Converter (ADC) allowsconversion of an analog input signal to a 10-bit binaryrepresentation of that signal. This device uses analoginputs, which are multiplexed into a single sample andhold circuit. The output of the sample and hold isconnected to the input of the converter. The convertergenerates a 10-bit binary result via successiveapproximation and stores the conversion result into theADC result registers (ADRESH:ADRESL register pair).Figure 15-1 shows the block diagram of the ADC.The ADC voltage reference is software selectable to beeither internally generated or externally supplied.The ADC can generate an interrupt upon completion ofa conversion. This interrupt can be used to wake-up thedevice from Sleep.FIGURE 15-1:ADC BLOCK DIAGRAMVDDADPREF = 00VREF+ ADPREF = 10AN000000VREF+/AN100001AN200010AN300011Reserved 00100VREF+VREF- = VSSADCGO/DONE10Reserved 11100Temp Indicator11101DAC 11110FVR Buffer111111ADONVSSADFM0 = Left Justify1 = Right JustifyADRESH16ADRESLCHSNote 1:When ADON = 0, all multiplexer inputs are disconnected. 2011 Microchip Technology Inc. Preliminary DS41615A-page 113

PIC12(L)F150115.1 ADC ConfigurationWhen configuring and using the ADC the followingfunctions must be considered:• Port configuration• Channel selection• ADC voltage reference selection• ADC conversion clock source• Interrupt control• Result formatting15.1.1 PORT CONFIGURATIONThe ADC can be used to convert both analog anddigital signals. When converting analog signals, the I/Opin should be configured for analog by setting theassociated TRIS and ANSEL bits. Refer toSection 11.0 “I/O Ports” for more information.Note:Analog voltages on any pin that is definedas a digital input may cause the input bufferto conduct excess current.15.1.2 CHANNEL SELECTIONThere are 7 channel selections available:• AN pins• Temperature Indicator• DAC• FVR (Fixed Voltage Reference) OutputRefer to Section 13.0 “Fixed Voltage Reference (FVR)”and Section 14.0 “Temperature Indicator Module” formore information on these channel selections.The CHS bits of the ADCON0 register determine whichchannel is connected to the sample and hold circuit.When changing channels, a delay is required beforestarting the next conversion. Refer to Section 15.2“ADC Operation” for more information.15.1.4 CONVERSION CLOCKThe source of the conversion clock is software selectablevia the ADCS bits of the ADCON1 register. Thereare seven possible clock options:• FOSC/2• FOSC/4• FOSC/8• FOSC/16• FOSC/32• FOSC/64• FRC (dedicated internal oscillator)The time to complete one bit conversion is defined asTAD. One full 10-bit conversion requires 11.5 TAD periodsas shown in Figure 15-2.For correct conversion, the appropriate TAD specificationmust be met. Refer to the A/D conversion requirementsin Section 27.0 “Electrical Specifications” formore information. Table 15-1 gives examples of appropriateADC clock selections.Note:Unless using the FRC, any changes in thesystem clock frequency will change theADC clock frequency, which mayadversely affect the ADC result.15.1.3 ADC VOLTAGE REFERENCEThe ADPREF bits of the ADCON1 register providescontrol of the positive voltage reference. The positivevoltage reference can be:• VREF+ pin• VDDSee Section 13.0 “Fixed Voltage Reference (FVR)”for more details on the Fixed Voltage Reference.DS41615A-page 114 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIESADC Clock Period (TAD)Device Frequency (FOSC)ADCClock SourceADCS 20 MHz 16 MHz 8 MHz 4 MHz 1 MHzFOSC/2 000 100 ns (2) 125 ns (2) 250 ns (2) 500 ns (2) 2.0 sFOSC/4 100 200 ns (2) 250 ns (2) 500 ns (2) 1.0 s 4.0 sFOSC/8 001 400 ns (2) 0.5 s (2) 1.0 s 2.0 s 8.0 s (3)FOSC/16 101 800 ns 1.0 s 2.0 s 4.0 s 16.0 s (3)FOSC/32 010 1.6 s 2.0 s 4.0 s 8.0 s (3) 32.0 s (3)FOSC/64 110 3.2 s 4.0 s 8.0 s (3) 16.0 s (3) 64.0 s (3)FRC x11 1.0-6.0 s (1,4) 1.0-6.0 s (1,4) 1.0-6.0 s (1,4) 1.0-6.0 s (1,4) 1.0-6.0 s (1,4)Legend: Shaded cells are outside of recommended range.Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.2: These values violate the minimum required TAD time.3: For faster conversion times, the selection of another clock source is recommended.4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from thesystem clock FOSC. However, the FRC clock source must be used when conversions are to be performed with thedevice in Sleep mode.FIGURE 15-2:ANALOG-TO-DIGITAL CONVERSION TAD CYCLESTCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11Conversion startsb9 b8 b7 b6 b5 b4 b3 b2 b1Holding capacitor is disconnected from analog input (typically 100 ns)b0Set GO bitOn the following cycle:ADRESH:ADRESL is loaded, GO bit is cleared,ADIF bit is set, holding capacitor is connected to analog input. 2011 Microchip Technology Inc. Preliminary DS41615A-page 115

PIC12(L)F150115.1.5 INTERRUPTSThe ADC module allows for the ability to generate aninterrupt upon completion of an Analog-to-Digitalconversion. The ADC Interrupt Flag is the ADIF bit inthe PIR1 register. The ADC Interrupt Enable is theADIE bit in the PIE1 register. The ADIF bit must becleared in software.Note 1: The ADIF bit is set at the completion ofevery conversion, regardless of whetheror not the ADC interrupt is enabled.2: The ADC operates during Sleep onlywhen the FRC oscillator is selected.This interrupt can be generated while the device isoperating or while in Sleep. If the device is in Sleep, theinterrupt will wake-up the device. Upon waking fromSleep, the next instruction following the SLEEP instructionis always executed. If the user is attempting towake-up from Sleep and resume in-line code execution,the GIE and PEIE bits of the INTCON registermust be disabled. If the GIE and PEIE bits of theINTCON register are enabled, execution will switch tothe Interrupt Service Routine.15.1.6 RESULT FORMATTINGThe 10-bit A/D conversion result can be supplied in twoformats, left justified or right justified. The ADFM bit ofthe ADCON1 register controls the output format.Figure 15-3 shows the two output formats.FIGURE 15-3:10-BIT A/D CONVERSION RESULT FORMATADRESHADRESL(ADFM = 0) MSB LSBbit 7 bit 0 bit 7 bit 010-bit A/D Result Unimplemented: Read as ‘0’(ADFM = 1) MSB LSBbit 7 bit 0 bit 7 bit 0Unimplemented: Read as ‘0’10-bit A/D ResultDS41615A-page 116 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150115.2 ADC Operation15.2.1 STARTING A CONVERSIONTo enable the ADC module, the ADON bit of theADCON0 register must be set to a ‘1’. Setting the GO/DONE bit of the ADCON0 register to a ‘1’ will start theAnalog-to-Digital conversion.Note:15.2.2 COMPLETION OF A CONVERSIONWhen the conversion is complete, the ADC module will:• Clear the GO/DONE bit• Set the ADIF Interrupt Flag bit• Update the ADRESH and ADRESL registers withnew conversion result15.2.3 TERMINATING A CONVERSIONIf a conversion must be terminated before completion,the GO/DONE bit can be cleared in software. TheADRESH and ADRESL registers will be updated withthe partially complete Analog-to-Digital conversionsample. Incomplete bits will match the last bitconverted.Note:The GO/DONE bit should not be set in thesame instruction that turns on the ADC.Refer to Section 15.2.6 “A/D ConversionProcedure”.A device Reset forces all registers to theirReset state. Thus, the ADC module isturned off and any pending conversion isterminated.15.2.4 ADC OPERATION DURING SLEEPThe ADC module can operate during Sleep. Thisrequires the ADC clock source to be set to the FRCoption. When the FRC clock source is selected, theADC waits one additional instruction before starting theconversion. This allows the SLEEP instruction to beexecuted, which can reduce system noise during theconversion. If the ADC interrupt is enabled, the devicewill wake-up from Sleep when the conversioncompletes. If the ADC interrupt is disabled, the ADCmodule is turned off after the conversion completes,although the ADON bit remains set.When the ADC clock source is something other thanFRC, a SLEEP instruction causes the present conversionto be aborted and the ADC module is turned off,although the ADON bit remains set.15.2.5 AUTO-CONVERSION TRIGGERThe auto-conversion trigger allows periodic ADC measurementswithout software intervention. When a risingedge of the selected source occurs, the GO/DONE bitis set by hardware.The auto-conversion trigger source is selected with theTRIGSEL bits of the ADCON2 register.Using the auto-conversion trigger does not assureproper ADC timing. It is the user’s responsibility toensure that the ADC timing requirements are met.Auto-conversion sources are:• TMR0• TMR1• TMR2• C1• CLC1• CLC2 2011 Microchip Technology Inc. Preliminary DS41615A-page 117

PIC12(L)F150115.2.6 A/D CONVERSION PROCEDUREThis is an example procedure for using the ADC toperform an Analog-to-Digital conversion:1. Configure Port:• Disable pin output driver (Refer to the TRISregister)• Configure pin as analog (Refer to the ANSELregister)2. Configure the ADC module:• Select ADC conversion clock• Configure voltage reference• Select ADC input channel• Turn on ADC module3. Configure ADC interrupt (optional):• Clear ADC interrupt flag• Enable ADC interrupt• Enable peripheral interrupt• Enable global interrupt (1)4. Wait the required acquisition time (2) .5. Start conversion by setting the GO/DONE bit.6. Wait for ADC conversion to complete by one ofthe following:• Polling the GO/DONE bit• Waiting for the ADC interrupt (interruptsenabled)7. Read ADC Result.8. Clear the ADC interrupt flag (required if interruptis enabled).EXAMPLE 15-1:A/D CONVERSION;This code block configures the ADC;for polling, Vdd and Vss references, Frc;clock and AN0 input.;;Conversion start & polling for completion; are included.;BANKSEL ADCON1 ;MOVLW B’11110000’ ;Right justify, Frc;clockMOVWF ADCON1 ;Vdd and Vss Vref+BANKSEL TRISA ;BSF TRISA,0 ;Set RA0 to inputBANKSEL ANSEL ;BSF ANSEL,0 ;Set RA0 to analogBANKSEL ADCON0 ;MOVLW B’00000001’ ;Select channel AN0MOVWF ADCON0 ;Turn ADC OnCALL SampleTime ;Acquisiton delayBSF ADCON0,ADGO ;Start conversionBTFSC ADCON0,ADGO ;Is conversion done?GOTO $-1 ;No, test againBANKSEL ADRESH ;MOVF ADRESH,W ;Read upper 2 bitsMOVWF RESULTHI ;store in GPR spaceBANKSEL ADRESL ;MOVF ADRESL,W ;Read lower 8 bitsMOVWF RESULTLO ;Store in GPR spaceNote 1: The global interrupt can be disabled if theuser is attempting to wake-up from Sleepand resume in-line code execution.2: Refer to Section 15.3 “A/D AcquisitionRequirements”.DS41615A-page 118 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150115.2.7 ADC REGISTER DEFINITIONSThe following registers are used to control theoperation of the ADC.REGISTER 15-1: ADCON0: A/D CONTROL REGISTER 0U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0— CHS GO/DONE ADONbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7 Unimplemented: Read as ‘0’bit 6-2 CHS: Analog Channel Select bits00000 =AN000001 =AN100010 =AN200011 =AN300100 = Reserved. No channel connected.•••11100 = Reserved. No channel connected.11101 = Temperature Indicator (1)11110 = DAC (Digital-to-Analog Converter) (2)11111 = FVR (Fixed Voltage Reference) Buffer 1 Output (3)bit 1bit 0GO/DONE: A/D Conversion Status bit1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.This bit is automatically cleared by hardware when the A/D conversion has completed.0 = A/D conversion completed/not in progressADON: ADC Enable bit1 = ADC is enabled0 = ADC is disabled and consumes no operating currentNote 1: See Section 14.0 “Temperature Indicator Module” for more information.2: See Section 16.0 “Digital-to-Analog Converter (DAC) Module” for more information.3: See Section 13.0 “Fixed Voltage Reference (FVR)” for more information. 2011 Microchip Technology Inc. Preliminary DS41615A-page 119

PIC12(L)F1501REGISTER 15-2: ADCON1: A/D CONTROL REGISTER 1R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0ADFM ADCS — — ADPREFbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7 ADFM: A/D Result Format Select bit1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result isloaded.0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result isloaded.bit 6-4 ADCS: A/D Conversion Clock Select bits000 = FOSC/2001 = FOSC/8010 = FOSC/32011 = FRC (clock supplied from a dedicated RC oscillator)100 = FOSC/4101 = FOSC/16110 = FOSC/64111 = FRC (clock supplied from a dedicated RC oscillator)bit 3-2 Unimplemented: Read as ‘0’bit 1-0 ADPREF: A/D Positive Voltage Reference Configuration bits00 =VREF+ is connected to VDD01 = Reserved10 =VREF+ is connected to external VREF+ pin (1)11 = ReservedNote 1:When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltagespecification exists. See Section 27.0 “Electrical Specifications” for details.DS41615A-page 120 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501REGISTER 15-3: ADCON2: A/D CONTROL REGISTER 2R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0TRIGSEL — — — —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-4 TRIGSEL: Auto-Conversion Trigger Selection bits (1)0000 = No auto-conversion trigger selected0001 = Reserved0010 = Reserved0011 = TMR0 Overflow (2)0100 = TMR1 Overflow (2)0101 = TMR2 Match to PR2 (2)0110 = C1OUT0111 = Reserved1000 = CLC11001 = CLC21010 = Reserved1011 = Reserved1100 = Reserved1101 = Reserved1110 = Reserved1111 = Reservedbit 3-0 Unimplemented: Read as ‘0’Note 1: This is a rising edge sensitive input for all sources.2: Signal also sets its corresponding interrupt flag. 2011 Microchip Technology Inc. Preliminary DS41615A-page 121

PIC12(L)F1501REGISTER 15-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/uADRESbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-0ADRES: ADC Result Register bitsUpper 8 bits of 10-bit conversion resultREGISTER 15-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/uADRES — — — — — —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-6bit 5-0ADRES: ADC Result Register bitsLower 2 bits of 10-bit conversion resultReserved: Do not use.DS41615A-page 122 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501REGISTER 15-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u— — — — — — ADRESbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-2bit 1-0Reserved: Do not use.ADRES: ADC Result Register bitsUpper 2 bits of 10-bit conversion resultREGISTER 15-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/uADRESbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-0ADRES: ADC Result Register bitsLower 8 bits of 10-bit conversion result 2011 Microchip Technology Inc. Preliminary DS41615A-page 123

PIC12(L)F150115.3 A/D Acquisition RequirementsFor the ADC to meet its specified accuracy, the chargeholding capacitor (CHOLD) must be allowed to fullycharge to the input channel voltage level. The AnalogInput model is shown in Figure 15-4. The sourceimpedance (RS) and the internal sampling switch (RSS)impedance directly affect the time required to chargethe capacitor CHOLD. The sampling switch (RSS)impedance varies over the device voltage (VDD), referto Figure 15-4. The maximum recommendedimpedance for analog sources is 10 k. As thesource impedance is decreased, the acquisition timemay be decreased. After the analog input channel isselected (or changed), an A/D acquisition must bedone before the conversion can be started. To calculatethe minimum acquisition time, Equation 15-1 may beused. This equation assumes that 1/2 LSb error is used(1,024 steps for the ADC). The 1/2 LSb error is themaximum error allowed for the ADC to meet itsspecified resolution.EQUATION 15-1:Assumptions:ACQUISITION TIME EXAMPLETemperature = 50°C and external impedance of 10k 5.0V VDDTACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient= TAMP + TC + TCOFF= 2µs + TC + Temperature - 25°C0.05µs/°CThe value for TC can be approximated with the following equations:VAPPLIED 1 1– -------------------------- 2 n+1 = VCHOLD–1;[1] VCHOLD charged to within 1/2 lsbVAPPLIED1 – e–TC---------RC=VCHOLD;[2] VCHOLD charge response to VAPPLIEDVAPPLIED1 – e–Tc--------RC=VAPPLIED 11– -------------------------- 2 n+1 – 1;combining [1] and [2]Note: Where n = number of bits of the ADC.Solving for TC:Therefore:–= + + ln(1/2047)= – 12.5pF1k + 7k + 10kln(0.0004885)TC CHOLD RIC RSS RS= 1.12µsTACQ = 5µs + 1.12µs +50°C- 25°C0.05µs/°C= 7.37µsNote 1: The reference voltage (VREF+) has no effect on the equation, since it cancels itself out.2: The charge holding capacitor (CHOLD) is not discharged after each conversion.3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pinleakage specification.DS41615A-page 124 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501FIGURE 15-4:ANALOG INPUT MODELRsAnalogInputpinVDDVT 0.6VRIC 1kSamplingSwitchSS RssVACPIN5 pFVT 0.6VI LEAKAGE (1)CHOLD = 10 pFVREF-Legend:CHOLDCPINI LEAKAGERICRSSSSVT= Sample/Hold Capacitance= Input Capacitance= Leakage current at the pin due tovarious junctions= Interconnect Resistance= Resistance of Sampling Switch= Sampling Switch= Threshold Voltage6V5VVDD 4V3V2VRSS567891011Sampling Switch(k)Note 1:Refer to Section 27.0 “Electrical Specifications”.FIGURE 15-5:ADC TRANSFER FUNCTIONFull-Scale Range3FFh3FEh3FDh3FChADC Output Code3FBh03h02h01h00hAnalog Input Voltage0.5 LSB1.5 LSBVREF-Zero-ScaleTransitionFull-ScaleTransitionVREF+ 2011 Microchip Technology Inc. Preliminary DS41615A-page 125

PIC12(L)F1501TABLE 15-2:SUMMARY OF REGISTERS ASSOCIATED WITH ADCName Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Registeron PageADCON0 — CHS GO/DONE ADON 119ADCON1 ADFM ADCS — — ADPREF 120ADCON2 TRIGSEL — — — — 121ADRESH A/D Result Register High 122, 123ADRESL A/D Result Register Low 122, 123ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 103INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66PIE1 TMR1GIE ADIE — — — — TMR2IE TMR1IE 67PIR1 TMR1GIF ADIF — — — — TMR2IF TMR1IF 70TRISA — — TRISA5 TRISA4—(1)TRISA2 TRISA1 TRISA0 102FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR ADFVR 110Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are notused for ADC module.Note 1: Unimplemented, read as ‘1’.DS41615A-page 126 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150116.0 DIGITAL-TO-ANALOGCONVERTER (DAC) MODULEThe Digital-to-Analog Converter supplies a variablevoltage reference, ratiometric with the input source,with 32 selectable output levels.The input of the DAC can be connected to:• External VREF+ pin• VDD supply voltageThe output of the DAC can be configured to supply areference voltage to the following:• Comparator positive input• ADC input channel• DACOUT1 pin• DACOUT2 pinThe Digital-to-Analog Converter (DAC) can be enabledby setting the DACEN bit of the DACCON0 register.16.1 Output Voltage SelectionThe DAC has 32 voltage level ranges. The 32 levelsare set with the DACR bits of the DACCON1register.The DAC output voltage is determined by the followingequations:EQUATION 16-1:DAC OUTPUT VOLTAGEIF DACEN = 1DACR4:0VOUT = VSOURCE+ – VSOURCE------------------------------ 2 5 + VSOURCE-IF DACEN = 0 and DACLPS = 1 and DACR[4:0] = 11111VOUT = VSOURCE +IF DACEN = 0 and DACLPS = 0 and DACR[4:0] = 00000VOUT = VSOURCE –VSOURCE+ = VDD, VREF, or FVR BUFFER 2VSOURCE- = VSS16.2 Ratiometric Output LevelThe DAC output value is derived using a resistor ladderwith each end of the ladder tied to a positive andnegative voltage reference input source. If the voltageof either input source fluctuates, a similar fluctuation willresult in the DAC output value.The value of the individual resistors within the laddercan be found in Section 27.0 “ElectricalSpecifications”.16.3 DAC Voltage Reference OutputThe DAC voltage can be output to the DACOUT1 andDACOUT2 pins by setting the respective DACOE1 andDACOE2 pins of the DACCON0 register. Selecting theDAC reference voltage for output on either DACOUTxpin automatically overrides the digital output buffer anddigital input threshold detector functions of that pin.Reading the DACOUTx pin when it has been configuredfor DAC reference voltage output will alwaysreturn a ‘0’.Due to the limited current drive capability, a buffer mustbe used on the DAC voltage reference output forexternal connections to either DACOUTx pin.Figure 16-2 shows an example buffering technique. 2011 Microchip Technology Inc. Preliminary DS41615A-page 127

PIC12(L)F1501FIGURE 16-1:DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAMDigital-to-Analog Converter (DAC)VDDVREF+VSOURCE+R5DACRDACPSSRDACENRR32StepsRR32-to-1 MUXDAC(To Comparator andADC Module)RRDACOUT1DACOE1VSOURCE-DACOUT2DACOE2FIGURE 16-2:VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLEPIC ® MCUDACModuleRVoltageReferenceOutputImpedanceDACOUTX+–Buffered DAC OutputDS41615A-page 128 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150116.4 Operation During SleepWhen the device wakes up from Sleep through aninterrupt or a Watchdog Timer time-out, the contents ofthe DACCON0 register are not affected. To minimizecurrent consumption in Sleep mode, the voltagereference should be disabled.16.5 Effects of a ResetA device Reset affects the following:• DAC is disabled.• DAC output voltage is removed from theDACOUT pin.• The DACR range select bits are cleared. 2011 Microchip Technology Inc. Preliminary DS41615A-page 129

PIC12(L)F150116.6 DAC Control RegistersREGISTER 16-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0 U-0DACEN — DACOE1 DACOE2 — DACPSS — —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7DACEN: DAC Enable bit1 = DAC is enabled0 = DAC is disabledbit 6 Unimplemented: Read as ‘0’bit 5DACOE1: DAC Voltage Output Enable bit1 = DAC voltage level is also an output on the DACOUT1 pin0 = DAC voltage level is disconnected from the DACOUT1 pinbit 4DACOE2: DAC Voltage Output Enable bit1 = DAC voltage level is also an output on the DACOUT2 pin0 = DAC voltage level is disconnected from the DACOUT2 pinbit 3 Unimplemented: Read as ‘0’bit 2DACPSS: DAC Positive Source Select bit1 = VREF+ pin0 = VDDbit 1-0 Unimplemented: Read as ‘0’REGISTER 16-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0— — — DACRbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-5 Unimplemented: Read as ‘0’bit 4-0DACR: DAC Voltage Output Select bitsTABLE 16-1:SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULEName Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Registeron pageFVRCON FVREN FVRRDY TSEN TSRNG CDAFVR ADFVR1 ADFVR0 161DACCON0 DACEN — DACOE1 DACOE2 — DACPSS — — 130DACCON1 — — — DACR 130Legend:— = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module.DS41615A-page 130 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150117.0 COMPARATOR MODULEFIGURE 17-1:SINGLE COMPARATORComparators are used to interface analog circuits to adigital circuit by comparing two analog voltages andproviding a digital indication of their relative magnitudes.Comparators are very useful mixed signal buildingblocks because they provide analog functionalityindependent of program execution. The analogcomparator module includes the following features:• Independent comparator control• Programmable input selection• Comparator output is available internally/externally• Programmable output polarity• Interrupt-on-change• Wake-up from Sleep• Programmable Speed/Power optimization• PWM shutdown• Programmable and fixed voltage reference17.1 Comparator OverviewA single comparator is shown in Figure 17-1 along withthe relationship between the analog input levels andthe digital output. When the analog voltage at VIN+ isless than the analog voltage at VIN-, the output of thecomparator is a digital low level. When the analogvoltage at VIN+ is greater than the analog voltage atVIN-, the output of the comparator is a digital high level.The comparators available for this device are located inTable 17-1.OutputNote:VIN+VIN-VIN-VIN++–OutputThe black areas of the output of thecomparator represents the uncertaintydue to input offsets and response time.TABLE 17-1:DevicePIC12F1501PIC12LF1501COMPARATOR AVAILABILITYPER DEVICEC1●● 2011 Microchip Technology Inc. Preliminary DS41615A-page 131

PIC12(L)F1501FIGURE 17-2:COMPARATOR MODULES SIMPLIFIED BLOCK DIAGRAMC12IN3-C12IN0-C12IN1-C12IN2-FVR Buffer2CxNCH3CXIN+DACFVR Buffer201MUX2 (2)34CXPCH20MUX1 (2)23CxVNCxVP-+CxONCxON (1)Note 1: When CxON = 0, the comparator will produce a ‘0’ at the output.2: When CxON = 0, all multiplexer inputs are disconnected.CxCxSPCxHYSCXPOL(from Timer1)T1CLKInterruptInterruptQ1DDENQdetdetQasync_CxOUTCXSYNCCxINTPCxINTN01CXOUTMCXOUTTo CWGCXOESYNC_CXOUTSet CxIFTo Data BusTRIS bitCXOUTTo Timer1,CLCx, ADCDS41615A-page 132 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150117.2 Comparator ControlEach comparator has 2 control registers: CMxCON0 andCMxCON1.The CMxCON0 registers (see Register 17-1) containControl and Status bits for the following:• Enable• Output selection• Output polarity• Speed/Power selection• Hysteresis enable• Output synchronizationThe CMxCON1 registers (see Register 17-2) containControl bits for the following:• Interrupt enable• Interrupt edge polarity• Positive input channel selection• Negative input channel selection17.2.1 COMPARATOR ENABLESetting the CxON bit of the CMxCON0 register enablesthe comparator for operation. Clearing the CxON bitdisables the comparator resulting in minimum currentconsumption.17.2.2 COMPARATOR OUTPUTSELECTIONThe output of the comparator can be monitored byreading either the CxOUT bit of the CMxCON0 registeror the MCxOUT bit of the CMOUT register. In order tomake the output available for an external connection,the following conditions must be true:• CxOE bit of the CMxCON0 register must be set• Corresponding TRIS bit must be cleared• CxON bit of the CMxCON0 register must be set17.2.3 COMPARATOR OUTPUT POLARITYInverting the output of the comparator is functionallyequivalent to swapping the comparator inputs. Thepolarity of the comparator output can be inverted bysetting the CxPOL bit of the CMxCON0 register.Clearing the CxPOL bit results in a non-inverted output.Table 17-2 shows the output state versus inputconditions, including polarity control.TABLE 17-2: COMPARATOR OUTPUTSTATE VS. INPUTCONDITIONSInput Condition CxPOL CxOUTCxVN > CxVP 0 0CxVN < CxVP 0 1CxVN > CxVP 1 1CxVN < CxVP 1 017.2.4 COMPARATOR SPEED/POWERSELECTIONThe trade-off between speed or power can be optimizedduring program execution with the CxSP controlbit. The default state for this bit is ‘1’ which selects thenormal speed mode. Device power consumption canbe optimized at the cost of slower comparator propagationdelay by clearing the CxSP bit to ‘0’.Note 1: The CxOE bit of the CMxCON0 registeroverrides the PORT data latch. Settingthe CxON bit of the CMxCON0 registerhas no impact on the port override.2: The internal output of the comparator islatched with each instruction cycle.Unless otherwise specified, externaloutputs are not latched. 2011 Microchip Technology Inc. Preliminary DS41615A-page 133

PIC12(L)F150117.3 Comparator HysteresisA selectable amount of separation voltage can beadded to the input pins of each comparator to provide ahysteresis function to the overall operation. Hysteresisis enabled by setting the CxHYS bit of the CMxCON0register.See Section 27.0 “Electrical Specifications” formore information.17.4 Timer1 Gate OperationThe output resulting from a comparator operation canbe used as a source for gate control of Timer1. SeeSection 19.5 “Timer1 Gate” for more information.This feature is useful for timing the duration or intervalof an analog event.It is recommended that the comparator output be synchronizedto Timer1. This ensures that Timer1 does notincrement while a change in the comparator is occurring.17.4.1 COMPARATOR OUTPUTSYNCHRONIZATIONThe output from a comparator can be synchronizedwith Timer1 by setting the CxSYNC bit of theCMxCON0 register.Once enabled, the comparator output is latched on thefalling edge of the Timer1 source clock. If a prescaler isused with Timer1, the comparator output is latched afterthe prescaling function. To prevent a race condition, thecomparator output is latched on the falling edge of theTimer1 clock source and Timer1 increments on therising edge of its clock source. See the ComparatorBlock Diagram (Figure 17-2) and the Timer1 BlockDiagram (Figure 19-1) for more information.17.5 Comparator InterruptAn interrupt can be generated upon a change in theoutput value of the comparator for each comparator, arising edge detector and a falling edge detector arepresent.When either edge detector is triggered and its associatedenable bit is set (CxINTP and/or CxINTN bits ofthe CMxCON1 register), the Corresponding InterruptFlag bit (CxIF bit of the PIR2 register) will be set.To enable the interrupt, you must set the following bits:• CxON, CxPOL and CxSP bits of the CMxCON0register• CxIE bit of the PIE2 register• CxINTP bit of the CMxCON1 register (for a risingedge detection)• CxINTN bit of the CMxCON1 register (for a fallingedge detection)• PEIE and GIE bits of the INTCON registerThe associated interrupt flag bit, CxIF bit of the PIR2register, must be cleared in software. If another edge isdetected while this flag is being cleared, the flag will stillbe set at the end of the sequence.Note:Although a comparator is disabled, aninterrupt can be generated by changingthe output polarity with the CxPOL bit ofthe CMxCON0 register, or by switchingthe comparator on or off with the CxON bitof the CMxCON0 register.17.6 Comparator Positive InputSelectionConfiguring the CxPCH bits of the CMxCON1register directs an internal voltage reference or ananalog pin to the non-inverting input of the comparator:• CxIN+ analog pin• DAC• FVR (Fixed Voltage Reference)• VSS (Ground)See Section 13.0 “Fixed Voltage Reference (FVR)”for more information on the Fixed Voltage Referencemodule.See Section 16.0 “Digital-to-Analog Converter(DAC) Module” for more information on the DAC inputsignal.Any time the comparator is disabled (CxON = 0), allcomparator inputs are disabled.DS41615A-page 134 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150117.7 Comparator Negative InputSelectionThe CxNCH bits of the CMxCON0 register directone of the input sources to the comparator invertinginput.Note:To use CxIN+ and CxINx- pins as analoginput, the appropriate bits must be set inthe ANSEL register and the correspondingTRIS bits must also be set to disablethe output drivers.17.8 Comparator Response TimeThe comparator output is indeterminate for a period oftime after the change of an input source or the selectionof a new reference voltage. This period is referred to asthe response time. The response time of the comparatordiffers from the settling time of the voltage reference.Therefore, both of these times must be considered whendetermining the total response time to a comparatorinput change. See the Comparator and Voltage ReferenceSpecifications in Section 27.0 “Electrical Specifications”for more details.17.9 Analog Input ConnectionConsiderationsA simplified circuit for an analog input is shown inFigure 17-3. Since the analog input pins share theirconnection with a digital input, they have reversebiased ESD protection diodes to VDD and VSS. Theanalog input, therefore, must be between VSS and VDD.If the input voltage deviates from this range by morethan 0.6V in either direction, one of the diodes is forwardbiased and a latch-up may occur.A maximum source impedance of 10 k is recommendedfor the analog sources. Also, any external componentconnected to an analog input pin, such as a capacitor ora Zener diode, should have very little leakage current tominimize inaccuracies introduced.Note 1: When reading a PORT register, all pinsconfigured as analog inputs will read as a‘0’. Pins configured as digital inputs willconvert as an analog input, according tothe input specification.2: Analog levels on any pin defined as adigital input, may cause the input buffer toconsume more current than is specified. 2011 Microchip Technology Inc. Preliminary DS41615A-page 135

PIC12(L)F1501FIGURE 17-3:ANALOG INPUT MODELRs < 10KAnalogInputpinVDDVT 0.6VRICTo ComparatorVACPIN5 pFVT 0.6VILEAKAGE (1)VssLegend: CPIN = Input CapacitanceILEAKAGE = Leakage Current at the pin due to various junctionsRIC = Interconnect ResistanceRS = Source ImpedanceVA = Analog VoltageVT = Threshold VoltageNote 1:See Section 27.0 “Electrical Specifications”.DS41615A-page 136 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501REGISTER 17-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 U-0 R/W-1/1 R/W-0/0 R/W-0/0CxON CxOUT CxOE CxPOL — CxSP CxHYS CxSYNCbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7 CxON: Comparator Enable bit1 = Comparator is enabled and consumes no active power0 = Comparator is disabledbit 6 CxOUT: Comparator Output bitIf CxPOL = 1 (inverted polarity):1 = CxVP < CxVN0 = CxVP > CxVNIf CxPOL = 0 (non-inverted polarity):1 = CxVP > CxVN0 = CxVP < CxVNbit 5 CxOE: Comparator Output Enable bit1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actuallydrive the pin. Not affected by CxON.0 = CxOUT is internal onlybit 4 CxPOL: Comparator Output Polarity Select bit1 = Comparator output is inverted0 = Comparator output is not invertedbit 3 Unimplemented: Read as ‘0’bit 2 CxSP: Comparator Speed/Power Select bit1 = Comparator operates in normal power, higher speed mode0 = Comparator operates in low-power, low-speed modebit 1 CxHYS: Comparator Hysteresis Enable bit1 = Comparator hysteresis enabled0 = Comparator hysteresis disabledbit 0 CxSYNC: Comparator Output Synchronous Mode bit1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.Output updated on the falling edge of Timer1 clock source.0 = Comparator output to Timer1 and I/O pin is asynchronous. 2011 Microchip Technology Inc. Preliminary DS41615A-page 137

PIC12(L)F1501REGISTER 17-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0CxINTP CxINTN CxPCH — CxNCHbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit0 = No interrupt flag will be set on a positive going edge of the CxOUT bitbit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bits1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit0 = No interrupt flag will be set on a negative going edge of the CxOUT bitbit 5-4 CxPCH: Comparator Positive Input Channel Select bits11 = CxVP connects to VSS10 = CxVP connects to FVR Voltage Reference01 = CxVP connects to DAC Voltage Reference00 = CxVP connects to CxIN+ pinbit 3 Unimplemented: Read as ‘0’bit 2-0 CxNCH: Comparator Negative Input Channel Select bits111 = Reserved110 = Reserved101 = Reserved100 = CxVN connects to FVR Voltage reference011 = CxVN connects to C12IN3- pin010 = CxVN connects to C12IN2- pin001 = CxVN connects to C12IN1- pin000 = CxVN connects to C12IN0- pinREGISTER 17-3:CMOUT: COMPARATOR OUTPUT REGISTERU-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0/0— — — — — — — MC1OUTbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-1 Unimplemented: Read as ‘0’bit 0 MC1OUT: Mirror Copy of C1OUT bitDS41615A-page 138 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501TABLE 17-3:SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULEName Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Registeron PageANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 103CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 137CM1CON1 C1NTP C1INTN C1PCH — C1NCH 138CMOUT — — — — — — — MC1OUT 138DACCON0 DACEN — DACOE1 DACOE2 — DACPSS — — 130DACCON1 — — — DACR 130FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR ADFVR 110INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66PIE2 — — C1IE — — NCO1IE — — 68PIR2 — — C1IF — — NCO1IF — — 71PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 102LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 103TRISA — — TRISA5 TRISA4 — (1) TRISA2 TRISA1 TRISA0 102Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.Note 1: Unimplemented, read as ‘1’. 2011 Microchip Technology Inc. Preliminary DS41615A-page 139

PIC12(L)F1501NOTES:DS41615A-page 140 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150118.0 TIMER0 MODULEThe Timer0 module is an 8-bit timer/counter with thefollowing features:• 8-bit timer/counter register (TMR0)• 8-bit prescaler (independent of Watchdog Timer)• Programmable internal or external clock source• Programmable external clock edge selection• Interrupt on overflow• TMR0 can be used to gate Timer1Figure 18-1 is a block diagram of the Timer0 module.18.1.2 8-BIT COUNTER MODEIn 8-Bit Counter mode, the Timer0 module will incrementon every rising or falling edge of the T0CKI pin.8-Bit Counter mode using the T0CKI pin is selected bysetting the TMR0CS bit in the OPTION_REG register to‘1’.The rising or falling transition of the incrementing edgefor either input source is determined by the TMR0SE bitin the OPTION_REG register.18.1 Timer0 OperationThe Timer0 module can be used as either an 8-bit timeror an 8-bit counter.18.1.1 8-BIT TIMER MODEThe Timer0 module will increment every instructioncycle, if used without a prescaler. 8-Bit Timer mode isselected by clearing the TMR0CS bit of theOPTION_REG register.When TMR0 is written, the increment is inhibited fortwo instruction cycles immediately following the write.Note:The value written to the TMR0 registercan be adjusted, in order to account forthe two instruction cycle delay whenTMR0 is written.FIGURE 18-1:BLOCK DIAGRAM OF THE TIMER0FOSC/4T0CKITMR0SE01TMR0CS8-bitPrescaler10PSASync2 TCYData Bus8TMR0Set Flag bit TMR0IFon OverflowOverflow to Timer18PS 2011 Microchip Technology Inc. Preliminary DS41615A-page 141

PIC12(L)F150118.1.3 SOFTWARE PROGRAMMABLEPRESCALERA software programmable prescaler is available forexclusive use with Timer0. The prescaler is enabled byclearing the PSA bit of the OPTION_REG register.Note:There are 8 prescaler options for the Timer0 moduleranging from 1:2 to 1:256. The prescale values areselectable via the PS bits of the OPTION_REGregister. In order to have a 1:1 prescaler value for theTimer0 module, the prescaler must be disabled by settingthe PSA bit of the OPTION_REG register.The prescaler is not readable or writable. All instructionswriting to the TMR0 register will clear the prescaler.18.1.4 TIMER0 INTERRUPTTimer0 will generate an interrupt when the TMR0register overflows from FFh to 00h. The TMR0IFinterrupt flag bit of the INTCON register is set everytime the TMR0 register overflows, regardless ofwhether or not the Timer0 interrupt is enabled. TheTMR0IF bit can only be cleared in software. The Timer0interrupt enable is the TMR0IE bit of the INTCONregister.Note:The Watchdog Timer (WDT) uses its ownindependent prescaler.The Timer0 interrupt cannot wake theprocessor from Sleep since the timer isfrozen during Sleep.18.1.5 8-BIT COUNTER MODESYNCHRONIZATIONWhen in 8-Bit Counter mode, the incrementing edge onthe T0CKI pin must be synchronized to the instructionclock. Synchronization can be accomplished bysampling the prescaler output on the Q2 and Q4 cyclesof the instruction clock. The high and low periods of theexternal clocking source must meet the timingrequirements as shown in Section 27.0 “ElectricalSpecifications”.18.1.6 OPERATION DURING SLEEPTimer0 cannot operate while the processor is in Sleepmode. The contents of the TMR0 register will remainunchanged while the processor is in Sleep mode.DS41615A-page 142 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150118.2 Option and Timer0 Control RegisterREGISTER 18-1:OPTION_REG: OPTION REGISTERR/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1WPUEN INTEDG TMR0CS TMR0SE PSA PSbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7bit 6bit 5bit 4bit 3bit 2-0WPUEN: Weak Pull-Up Enable bit1 = All weak pull-ups are disabled (except MCLR, if it is enabled)0 = Weak pull-ups are enabled by individual WPUx latch valuesINTEDG: Interrupt Edge Select bit1 = Interrupt on rising edge of INT pin0 = Interrupt on falling edge of INT pinTMR0CS: Timer0 Clock Source Select bit1 = Transition on T0CKI pin0 = Internal instruction cycle clock (FOSC/4)TMR0SE: Timer0 Source Edge Select bit1 = Increment on high-to-low transition on T0CKI pin0 = Increment on low-to-high transition on T0CKI pinPSA: Prescaler Assignment bit1 = Prescaler is not assigned to the Timer0 module0 = Prescaler is assigned to the Timer0 modulePS: Prescaler Rate Select bitsBit ValueTimer0 Rate0000010100111001011101111 : 21 : 41 : 81 : 161 : 321 : 641 : 1281 : 256TABLE 18-1:SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Registeron PageADCON2 TRIGSEL — — — — 121INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS 143TMR0 Holding Register for the 8-bit Timer0 Count 141*TRISA — — TRISA5 TRISA4 — (1) TRISA2 TRISA1 TRISA0 102Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.* Page provides register information.Note 1: Unimplemented, read as ‘1’. 2011 Microchip Technology Inc. Preliminary DS41615A-page 143

PIC12(L)F1501NOTES:DS41615A-page 144 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150119.0 TIMER1 MODULE WITH GATECONTROLThe Timer1 module is a 16-bit timer/counter with thefollowing features:• 16-bit timer/counter register pair (TMR1H:TMR1L)• Programmable internal or external clock source• 2-bit prescaler• Optionally synchronized comparator out• Multiple Timer1 gate (count enable) sources• Interrupt on overflow• Wake-up on overflow (external clock,Asynchronous mode only)• Special Event Trigger• Selectable Gate Source Polarity• Gate Toggle mode• Gate Single-Pulse mode• Gate Value Status• Gate Event InterruptFigure 19-1 is a block diagram of the Timer1 module.FIGURE 19-1:TIMER1 BLOCK DIAGRAMT1GSST1G 00From Timer0Overflowsync_C1OUTReservedT1GPOL011011TMR1ONT1GTMt1g_inDCKRQQ01T1GGO/DONET1GSPMSingle PulseAcq. Control01T1GVALQ1DTMR1GEENInterruptdetQData BusRDT1GCONSetTMR1GIFSet flag bitTMR1IF onOverflowTo ADC Auto-ConversionTMR1HTMR1 (2)TMR1LQENDT1CLKTMR1ON0SynchronizedClock Input1TMR1CST1SYNCT1CKI(1)LFINTOSCFOSCInternalClockFOSC/4InternalClock11100100Prescaler1, 2, 4, 82T1CKPSFOSC/2InternalClockSynchronize (3)detSleep inputNote 1: ST Buffer is high speed type when using T1CKI.2: Timer1 register increments on rising edge.3: Synchronize does not operate while in Sleep. 2011 Microchip Technology Inc. Preliminary DS41615A-page 145

PIC12(L)F150119.1 Timer1 OperationThe Timer1 module is a 16-bit incrementing counterwhich is accessed through the TMR1H:TMR1L registerpair. Writes to TMR1H or TMR1L directly update thecounter.When used with an internal clock source, the module isa timer and increments on every instruction cycle.When used with an external clock source, the modulecan be used as either a timer or counter and incrementson every selected edge of the external source.Timer1 is enabled by configuring the TMR1ON andTMR1GE bits in the T1CON and T1GCON registers,respectively. Table 19-1 displays the Timer1 enableselections.TABLE 19-1:TMR1ONTIMER1 ENABLESELECTIONSTMR1GETimer1Operation0 0 Off0 1 Off1 0 Always On1 1 Count Enabled19.2 Clock Source SelectionThe TMR1CS bits of the T1CON register are usedto select the clock source for Timer1. Table 19-2displays the clock source selections.19.2.1 INTERNAL CLOCK SOURCEWhen the internal clock source is selected theTMR1H:TMR1L register pair will increment on multiplesof FOSC as determined by the Timer1 prescaler.When the FOSC internal clock source is selected, theTimer1 register value will increment by four counts everyinstruction clock cycle. Due to this condition, a 2 LSBerror in resolution will occur when reading the Timer1value. To utilize the full resolution of Timer1, anasynchronous input signal must be used to gate theTimer1 clock input.The following asynchronous sources may be used:• Asynchronous event on the T1G pin to Timer1gate19.2.2 EXTERNAL CLOCK SOURCEWhen the external clock source is selected, the Timer1module may work as a timer or a counter.When enabled to count, Timer1 is incremented on therising edge of the external clock input T1CKI. Theexternal clock source can be synchronized to themicrocontroller system clock or it can runasynchronously.Note:In Counter mode, a falling edge must beregistered by the counter prior to the firstincrementing rising edge after any one ormore of the following conditions:• Timer1 enabled after POR• Write to TMR1H or TMR1L• Timer1 is disabled• Timer1 is disabled (TMR1ON = 0)when T1CKI is high then Timer1 isenabled (TMR1ON=1) when T1CKI islow.TABLE 19-2: CLOCK SOURCE SELECTIONSTMR1CS T1OSCEN Clock Source11 x LFINTOSC10 0 External Clocking on T1CKI Pin01 x System Clock (FOSC)00 x Instruction Clock (FOSC/4)DS41615A-page 146 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150119.3 Timer1 PrescalerTimer1 has four prescaler options allowing 1, 2, 4 or 8divisions of the clock input. The T1CKPS bits of theT1CON register control the prescale counter. Theprescale counter is not directly readable or writable;however, the prescaler counter is cleared upon a write toTMR1H or TMR1L.19.4 Timer1 Operation inAsynchronous Counter ModeIf control bit T1SYNC of the T1CON register is set, theexternal clock input is not synchronized. The timerincrements asynchronously to the internal phaseclocks. If the external clock source is selected then thetimer will continue to run during Sleep and cangenerate an interrupt on overflow, which will wake-upthe processor. However, special precautions insoftware are needed to read/write the timer (seeSection 19.4.1 “Reading and Writing Timer1 inAsynchronous Counter Mode”).Note:When switching from synchronous toasynchronous operation, it is possible toskip an increment. When switching fromasynchronous to synchronous operation,it is possible to produce an additionalincrement.19.4.1 READING AND WRITING TIMER1 INASYNCHRONOUS COUNTERMODEReading TMR1H or TMR1L while the timer is runningfrom an external asynchronous clock will ensure a validread (taken care of in hardware). However, the usershould keep in mind that reading the 16-bit timer in two8-bit values itself, poses certain problems, since thetimer may overflow between the reads.For writes, it is recommended that the user simply stopthe timer and write the desired values. A writecontention may occur by writing to the timer registers,while the register is incrementing. This may produce anunpredictable value in the TMR1H:TMR1L register pair.When Timer1 Gate Enable mode is enabled, Timer1will increment on the rising edge of the Timer1 clocksource. When Timer1 Gate Enable mode is disabled,no incrementing will occur and Timer1 will hold thecurrent count. See Figure 19-3 for timing details.TABLE 19-3:19.5.2 TIMER1 GATE SOURCESELECTIONTimer1 gate source selections are shown in Table 19-4.Source selection is controlled by the T1GSS bitsof the T1GCON register. The polarity for each availablesource is also selectable. Polarity selection is controlledby the T1GPOL bit of the T1GCON register.TABLE 19-4:TIMER1 GATE ENABLESELECTIONST1CLK T1GPOL T1G Timer1 Operation 0 0 Counts 0 1 Holds Count 1 0 Holds Count 1 1 CountsT1GSSTIMER1 GATE SOURCESTimer1 Gate Source00 Timer1 Gate Pin01 Overflow of Timer0(TMR0 increments from FFh to 00h)10 Comparator 1 Output sync_C1OUT(optionally synchronized comparator output)11 Reserved19.5 Timer1 GateTimer1 can be configured to count freely or the countcan be enabled and disabled using Timer1 gatecircuitry. This is also referred to as Timer1 Gate Enable.Timer1 gate can also be driven by multiple selectablesources.19.5.1 TIMER1 GATE ENABLEThe Timer1 Gate Enable mode is enabled by settingthe TMR1GE bit of the T1GCON register. The polarityof the Timer1 Gate Enable mode is configured usingthe T1GPOL bit of the T1GCON register. 2011 Microchip Technology Inc. Preliminary DS41615A-page 147

PIC12(L)F150119.5.2.1 T1G Pin Gate OperationThe T1G pin is one source for Timer1 Gate Control. Itcan be used to supply an external source to the Timer1gate circuitry.19.5.2.2 Timer0 Overflow Gate OperationWhen Timer0 increments from FFh to 00h, alow-to-high pulse will automatically be generated andinternally supplied to the Timer1 gate circuitry.19.5.3 TIMER1 GATE TOGGLE MODEWhen Timer1 Gate Toggle mode is enabled, it is possibleto measure the full-cycle length of a Timer1 gatesignal, as opposed to the duration of a single levelpulse.The Timer1 gate source is routed through a flip-flop thatchanges state on every incrementing edge of the signal.See Figure 19-4 for timing details.Timer1 Gate Toggle mode is enabled by setting theT1GTM bit of the T1GCON register. When the T1GTMbit is cleared, the flip-flop is cleared and held clear. Thisis necessary in order to control which edge ismeasured.Note:Enabling Toggle mode at the same timeas changing the gate polarity may result inindeterminate operation.19.5.5 TIMER1 GATE VALUE STATUSWhen Timer1 Gate Value Status is utilized, it is possibleto read the most current level of the gate control value.The value is stored in the T1GVAL bit in the T1GCONregister. The T1GVAL bit is valid even when the Timer1gate is not enabled (TMR1GE bit is cleared).19.5.6 TIMER1 GATE EVENT INTERRUPTWhen Timer1 Gate Event Interrupt is enabled, it is possibleto generate an interrupt upon the completion of agate event. When the falling edge of T1GVAL occurs,the TMR1GIF flag bit in the PIR1 register will be set. Ifthe TMR1GIE bit in the PIE1 register is set, then aninterrupt will be recognized.The TMR1GIF flag bit operates even when the Timer1gate is not enabled (TMR1GE bit is cleared).19.5.4 TIMER1 GATE SINGLE-PULSEMODEWhen Timer1 Gate Single-Pulse mode is enabled, it ispossible to capture a single pulse gate event. Timer1Gate Single-Pulse mode is first enabled by setting theT1GSPM bit in the T1GCON register. Next, theT1GGO/DONE bit in the T1GCON register must be set.The Timer1 will be fully enabled on the next incrementingedge. On the next trailing edge of the pulse, theT1GGO/DONE bit will automatically be cleared. No othergate events will be allowed to increment Timer1 until theT1GGO/DONE bit is once again set in software. SeeFigure 19-5 for timing details.If the Single Pulse Gate mode is disabled by clearing theT1GSPM bit in the T1GCON register, the T1GGO/DONEbit should also be cleared.Enabling the Toggle mode and the Single-Pulse modesimultaneously will permit both sections to worktogether. This allows the cycle times on the Timer1 gatesource to be measured. See Figure 19-6 for timingdetails.DS41615A-page 148 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150119.6 Timer1 InterruptThe Timer1 register pair (TMR1H:TMR1L) incrementsto FFFFh and rolls over to 0000h. When Timer1 rollsover, the Timer1 interrupt flag bit of the PIR1 register isset. To enable the interrupt on rollover, you must setthese bits:• TMR1ON bit of the T1CON register• TMR1IE bit of the PIE1 register• PEIE bit of the INTCON register• GIE bit of the INTCON registerThe interrupt is cleared by clearing the TMR1IF bit inthe Interrupt Service Routine.19.7.1 ALTERNATE PIN LOCATIONSThis module incorporates I/O pins that can be moved toother locations with the use of the alternate pin functionregister, APFCON. To determine which pins can bemoved and what their default locations are upon aReset, see Section 11.1 “Alternate Pin Function” formore information.Note:The TMR1H:TMR1L register pair and theTMR1IF bit should be cleared beforeenabling interrupts.19.7 Timer1 Operation During SleepTimer1 can only operate during Sleep when setup inAsynchronous Counter mode. In this mode, an externalcrystal or clock source can be used to increment thecounter. To set up the timer to wake the device:• TMR1ON bit of the T1CON register must be set• TMR1IE bit of the PIE1 register must be set• PEIE bit of the INTCON register must be set• T1SYNC bit of the T1CON register must be set• TMR1CS bits of the T1CON register must beconfiguredThe device will wake-up on an overflow and executethe next instructions. If the GIE bit of the INTCONregister is set, the device will call the Interrupt ServiceRoutine.Timer1 oscillator will continue to operate in Sleepregardless of the T1SYNC bit setting.FIGURE 19-2:TIMER1 INCREMENTING EDGET1CKI = 1when TMR1EnabledT1CKI = 0when TMR1EnabledNote 1: Arrows indicate counter increments.2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2011 Microchip Technology Inc. Preliminary DS41615A-page 149

PIC12(L)F1501FIGURE 19-3:TIMER1 GATE ENABLE MODETMR1GET1GPOLt1g_inT1CKIT1GVALTimer1 N N + 1 N + 2 N + 3 N + 4FIGURE 19-4:TIMER1 GATE TOGGLE MODETMR1GET1GPOLT1GTMt1g_inT1CKIT1GVALTimer1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8DS41615A-page 150 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501FIGURE 19-5:TIMER1 GATE SINGLE-PULSE MODETMR1GET1GPOLT1GSPMT1GGO/DONEt1g_inSet by softwareCounting enabled onrising edge of T1GCleared by hardware onfalling edge of T1GVALT1CKIT1GVALTimer1 N N + 1 N + 2TMR1GIFCleared by softwareSet by hardware onfalling edge of T1GVALCleared bysoftware 2011 Microchip Technology Inc. Preliminary DS41615A-page 151

PIC12(L)F1501FIGURE 19-6:TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODETMR1GET1GPOLT1GSPMT1GTMT1GGO/DONEt1g_inSet by softwareCounting enabled onrising edge of T1GCleared by hardware onfalling edge of T1GVALT1CKIT1GVALTimer1 N N + 1 N + 2N + 3N + 4TMR1GIFCleared by softwareSet by hardware onfalling edge of T1GVALCleared bysoftwareDS41615A-page 152 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150119.8 Timer1 Control RegistersREGISTER 19-1:T1CON: TIMER1 CONTROL REGISTERR/W-0/u R/W-0/u R/W-0/u R/W-0/u U-0 R/W-0/u U-0 R/W-0/uTMR1CS T1CKPS — T1SYNC — TMR1ONbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-6 TMR1CS: Timer1 Clock Source Select bits11 = Timer1 clock source is LFINTOSC10 = Timer1 clock source is T1CKI pin (on rising edge)01 = Timer1 clock source is system clock (FOSC)00 = Timer1 clock source is instruction clock (FOSC/4)bit 5-4 T1CKPS: Timer1 Input Clock Prescale Select bits11 = 1:8 Prescale value10 = 1:4 Prescale value01 = 1:2 Prescale value00 = 1:1 Prescale valuebit 3 Unimplemented: Read as ‘0’bit 2 T1SYNC: Timer1 Synchronization Control bit1 = Do not synchronize asynchronous clock input0 = Synchronize asynchronous clock input with system clock (FOSC)bit 1 Unimplemented: Read as ‘0’bit 0 TMR1ON: Timer1 On bit1 = Enables Timer10 = Stops Timer1 and clears Timer1 gate flip-flop 2011 Microchip Technology Inc. Preliminary DS41615A-page 153

PIC12(L)F1501REGISTER 19-2:T1GCON: TIMER1 GATE CONTROL REGISTERR/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/uTMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSSDONEbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardwarebit 7bit 6bit 5bit 4bit 3bit 2bit 0TMR1GE: Timer1 Gate Enable bitIf TMR1ON = 0:This bit is ignoredIf TMR1ON = 1:1 = Timer1 counting is controlled by the Timer1 gate function0 = Timer1 counts regardless of Timer1 gate functionT1GPOL: Timer1 Gate Polarity bit1 = Timer1 gate is active-high (Timer1 counts when gate is high)0 = Timer1 gate is active-low (Timer1 counts when gate is low)T1GTM: Timer1 Gate Toggle Mode bit1 = Timer1 Gate Toggle mode is enabled0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is clearedTimer1 gate flip-flop toggles on every rising edge.T1GSPM: Timer1 Gate Single-Pulse Mode bit1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate0 = Timer1 Gate Single-Pulse mode is disabledT1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge0 = Timer1 gate single-pulse acquisition has completed or has not been startedT1GVAL: Timer1 Gate Current State bitIndicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.Unaffected by Timer1 Gate Enable (TMR1GE).T1GSS: Timer1 Gate Source Select bits11 = Reserved10 = Comparator 1 optionally synchronized output (sync_C1OUT)01 = Timer0 overflow output00 = Timer1 gate pinDS41615A-page 154 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150119.8.1 ALTERNATE PIN LOCATIONSThis module incorporates I/O pins that can be moved toother locations with the use of the alternate pin functionregister, APFCON. To determine which pins can bemoved and what their default locations are upon aReset, see Section 11.1 “Alternate Pin Function” formore information.TABLE 19-5:SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Registeron PageANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 103APFCON CWG1BSEL CWG1ASEL — — T1GSEL — CLC1SEL NCO1SEL 100INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66PIE1 TMR1GIE ADIE — — — — TMR2IE TMR1IE 67PIR1 TMR1GIF ADIF — — — — TMR2IF TMR1IF 70TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count 149*TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count 149*TRISA — — TRISA5 TRISA4 — (1) TRISA2 TRISA1 TRISA0 102T1CON TMR1CS T1CKPS — T1SYNC — TMR1ON 153T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS 154DONELegend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.* Page provides register information.Note 1: Unimplemented, read as ‘1’. 2011 Microchip Technology Inc. Preliminary DS41615A-page 155

PIC12(L)F1501NOTES:DS41615A-page 156 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150120.0 TIMER2 MODULEThe Timer2 module incorporates the following features:• 8-bit Timer and Period registers (TMR2 and PR2,respectively)• Readable and writable (both registers)• Software programmable prescaler (1:1, 1:4, 1:16,and 1:64)• Software programmable postscaler (1:1 to 1:16)• Interrupt on TMR2 match with PR2, respectivelySee Figure 20-1 for a block diagram of Timer2.FIGURE 20-1:TIMER2 BLOCK DIAGRAMTMR2OutputSets Flagbit TMR2IFFOSC/4Prescaler1:1, 1:4, 1:16, 1:64TMR2Reset2T2CKPSComparatorPR2EQPostscaler1:1 to 1:164T2OUTPS 2011 Microchip Technology Inc. Preliminary DS41615A-page 157

PIC12(L)F150120.1 Timer2 OperationThe clock input to the Timer2 module is the systeminstruction clock (FOSC/4).TMR2 increments from 00h on each clock edge.A 4-bit counter/prescaler on the clock input allows directinput, divide-by-4 and divide-by-16 prescale options.These options are selected by the prescaler control bits,T2CKPS of the T2CON register. The value ofTMR2 is compared to that of the Period register, PR2, oneach clock cycle. When the two values match, thecomparator generates a match signal as the timeroutput. This signal also resets the value of TMR2 to 00hon the next cycle and drives the outputcounter/postscaler (see Section 20.2 “Timer2Interrupt”).The TMR2 and PR2 registers are both directly readableand writable. The TMR2 register is cleared on anydevice Reset, whereas the PR2 register initializes toFFh. Both the prescaler and postscaler counters arecleared on the following events:• a write to the TMR2 register• a write to the T2CON register• Power-on Reset (POR)• Brown-out Reset (BOR)• MCLR Reset• Watchdog Timer (WDT) Reset• Stack Overflow Reset• Stack Underflow Reset• RESET InstructionNote: TMR2 is not cleared when T2CON iswritten.20.3 Timer2 OutputThe unscaled output of TMR2 is available primarily tothe PWMx module, where it is used as a time base foroperation.20.4 Timer2 Operation During SleepTimer2 cannot be operated while the processor is inSleep mode. The contents of the TMR2 and PR2registers will remain unchanged while the processor isin Sleep mode.20.2 Timer2 InterruptTimer2 can also generate an optional device interrupt.The Timer2 output signal (TMR2-to-PR2 match)provides the input for the 4-bit counter/postscaler. Thiscounter generates the TMR2 match interrupt flag whichis latched in TMR2IF of the PIR1 register. The interruptis enabled by setting the TMR2 Match Interrupt Enablebit, TMR2IE of the PIE1 register.A range of 16 postscale options (from 1:1 through 1:16inclusive) can be selected with the postscaler controlbits, T2OUTPS, of the T2CON register.DS41615A-page 158 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501REGISTER 20-1:T2CON: TIMER2 CONTROL REGISTERU-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0— T2OUTPS TMR2ON T2CKPSbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7 Unimplemented: Read as ‘0’bit 6-3 T2OUTPS: Timer2 Output Postscaler Select bits0000 = 1:1 Postscaler0001 = 1:2 Postscaler0010 = 1:3 Postscaler0011 = 1:4 Postscaler0100 = 1:5 Postscaler0101 = 1:6 Postscaler0110 = 1:7 Postscaler0111 = 1:8 Postscaler1000 = 1:9 Postscaler1001 = 1:10 Postscaler1010 = 1:11 Postscaler1011 = 1:12 Postscaler1100 = 1:13 Postscaler1101 = 1:14 Postscaler1110 = 1:15 Postscaler1111 = 1:16 Postscalerbit 2 TMR2ON: Timer2 On bit1 = Timer2 is on0 = Timer2 is offbit 1-0 T2CKPS: Timer2 Clock Prescale Select bits00 = Prescaler is 101 = Prescaler is 410 = Prescaler is 1611 = Prescaler is 64 2011 Microchip Technology Inc. Preliminary DS41615A-page 159

PIC12(L)F1501TABLE 20-1:SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Registeron PageINTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66PIE1 TMR1GIE ADIE — — — — TMR2IE TMR1IE 67PIR1 TMR1GIF ADIF — — — — TMR2IF TMR1IF 70PR2 Timer2 Module Period Register 157*PWM1CON PWM1EN PWM1OE PWM1OUT PWM1POL — — — — 165PWM2CON PWM2EN PWM2OE PWM2OUT PWM2POL — — — — 165PWM3CON PWM3EN PWM3OE PWM3OUT PWM3POL — — — — 165PWM4CON PWM4EN PWM4OE PWM4OUT PWM4POL — — — — 165T2CON — T2OUTPS TMR2ON T2CKPS 159TMR2 Holding Register for the 8-bit TMR2 Count 157*Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.* Page provides register information.DS41615A-page 160 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150121.0 PULSE-WIDTH MODULATION(PWM) MODULEThe PWM module generates a Pulse-Width Modulatedsignal determined by the duty cycle, period, and resolutionthat are configured by the following registers:• PR2• T2CON• PWMxDCH• PWMxDCL• PWMxCONFigure 21-2 shows a simplified block diagram of PWMoperation.Figure 21-1 shows a typical waveform of the PWMsignal.For a step-by-step procedure on how to set up thismodule for PWM operation, refer to Section 21.1.9“Setup for PWM Operation using PWMx Pins”.FIGURE 21-1:PeriodPulse WidthTMR2 = 0PWM OUTPUTTMR2 = PR2TMR2 =PWMxDCH:PWMxDCLFIGURE 21-2:SIMPLIFIED PWM BLOCK DIAGRAMDuty Cycle registersPWMxDCLPWMxDCHPWMxOUTto other peripherals: CLC and CWGLatched(Not visible to user)Output Enable (PWMxOE)ComparatorRQ0TRIS ControlPWMxSQ1TMR2 ModuleTMR2(1)Output Polarity (PWMxPOL)ComparatorPR2Clear Timer,PWMx pin andlatch Duty CycleNote 1:8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted bythe Timer2 prescaler to create a 10-bit time base. 2011 Microchip Technology Inc. Preliminary DS41615A-page 161

PIC12(L)F150121.1 PWMx Pin ConfigurationAll PWM outputs are multiplexed with the PORT datalatch. The user must configure the pins as outputs byclearing the associated TRIS bits.Note:21.1.1 FUNDAMENTAL OPERATIONThe PWM module produces a 10-bit resolution output.Timer2 and PR2 set the period of the PWM. ThePWMxDCL and PWMxDCH registers configure theduty cycle. The period is common to all PWM modules,whereas the duty cycle is independently controlled.Note:All PWM outputs associated with Timer2 are set whenTMR2 is cleared. Each PWMx is cleared when TMR2is equal to the value specified in the correspondingPWMxDCH (8 MSb) and PWMxDCL (2 LSb) registers.When the value is greater than or equal to PR2,the PWM output is never cleared (100% duty cycle).Note:21.1.2 PWM OUTPUT POLARITYThe output polarity is inverted by setting the PWMxPOLbit of the PWMxCON register.21.1.3 PWM PERIODThe PWM period is specified by the PR2 register ofTimer2. The PWM period can be calculated using theformula of Equation 21-1.EQUATION 21-1:Clearing the PWMxOE bit will relinquishcontrol of the PWMx pin.The Timer2 postscaler is not used in thedetermination of the PWM frequency. Thepostscaler could be used to have a servoupdate rate at a different frequency thanthe PWM output.The PWMxDCH and PWMxDCL registersare double buffered. The buffers areupdated when Timer2 matches PR2. Careshould be taken to update both registersbefore the timer match occurs.PWM PERIODWhen TMR2 is equal to PR2, the following three eventsoccur on the next increment cycle:• TMR2 is cleared• The PWM output is active. (Exception: When thePWM duty cycle = 0%, the PWM output willremain inactive.)• The PWMxDCH and PWMxDCL register valuesare latched into the buffers.Note:21.1.4 PWM DUTY CYCLEThe PWM duty cycle is specified by writing a 10-bitvalue to the PWMxDCH and PWMxDCL register pair.The PWMxDCH register contains the eight MSbs andthe PWMxDCL, the two LSbs. The PWMxDCHand PWMxDCL registers can be written to at any time.Equation 21-2 is used to calculate the PWM pulsewidth.Equation 21-3 is used to calculate the PWM duty cycleratio.EQUATION 21-2:Pulse WidthEQUATION 21-3:The Timer2 postscaler has no effect onthe PWM operation.Note: TOSC = 1/FOSCPULSE WIDTH= PWMxDCH:PWMxDCL TOSC (TMR2 Prescale Value)DUTY CYCLE RATIOPWMxDCH:PWMxDCLDuty Cycle Ratio = ----------------------------------------------------------------------------------4PR2 + 1The 8-bit timer TMR2 register is concatenated with thetwo Least Significant bits of 1/FOSC, adjusted by theTimer2 prescaler to create the 10-bit time base. Thesystem clock is used if the Timer2 prescaler is set to1:1.PWM Period= PR2 + 14TOSC (TMR2 Prescale Value)Note:TOSC = 1/FOSCDS41615A-page 162 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150121.1.5 PWM RESOLUTIONThe resolution determines the number of available dutycycles for a given period. For example, a 10-bit resolutionwill result in 1024 discrete duty cycles, whereas an8-bit resolution will result in 256 discrete duty cycles.The maximum PWM resolution is 10 bits when PR2 is255. The resolution is a function of the PR2 registervalue as shown by Equation 21-4.EQUATION 21-4:Resolution=PWM RESOLUTIONlog ----------------------------------------- 4PR2 + 1log2bitsNote:If the pulse width value is greater than theperiod the assigned PWM pin(s) willremain unchanged.TABLE 21-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)PWM Frequency 0.31 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHzTimer Prescale (1, 4, 64) 64 4 1 1 1 1PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17Maximum Resolution (bits) 10 10 10 8 7 6.6TABLE 21-2:EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)PWM Frequency 0.31 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHzTimer Prescale (1, 4, 64) 64 4 1 1 1 1PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09Maximum Resolution (bits) 8 8 8 6 5 521.1.6 OPERATION IN SLEEP MODEIn Sleep mode, the TMR2 register will not incrementand the state of the module will not change. If thePWMx pin is driving a value, it will continue to drive thatvalue. When the device wakes up, TMR2 will continuefrom its previous state.21.1.7 CHANGES IN SYSTEM CLOCKFREQUENCYThe PWM frequency is derived from the system clockfrequency (FOSC). Any changes in the system clock frequencywill result in changes to the PWM frequency.Refer to Section 5.0 “Oscillator Module” for additionaldetails.21.1.8 EFFECTS OF RESETAny Reset will force all ports to Input mode and thePWM registers to their Reset states. 2011 Microchip Technology Inc. Preliminary DS41615A-page 163

PIC12(L)F150121.1.9 SETUP FOR PWM OPERATIONUSING PWMx PINSThe following steps should be taken when configuringthe module for PWM operation using the PWMx pins:1. Disable the PWMx pin output driver(s) by settingthe associated TRIS bit(s).2. Clear the PWMxCON register.3. Load the PR2 register with the PWM periodvalue.4. Clear the PWMxDCH register and bits ofthe PWMxDCL register.5. Configure and start Timer2:• Clear the TMR2IF interrupt flag bit of the PIR1register. See Note below.• Configure the T2CKPS bits of the T2CON registerwith the Timer2 prescale value.• Enable Timer2 by setting the TMR2ON bit of theT2CON register.6. Enable PWM output pin and wait until Timer2overflows, TMR2IF bit of the PIR1 register is set.See Note below.7. Enable the PWMx pin output driver(s) by clearingthe associated TRIS bit(s) and setting thePWMxOE bit of the PWMxCON register.8. Configure the PWM module by loading thePWMxCON register with the appropriate values.Note 1: In order to send a complete duty cycleand period on the first PWM output, theabove steps must be followed in the ordergiven. If it is not critical to start with acomplete PWM signal, then move Step 8to replace Step 4.2: For operation with other peripherals only,disable PWMx pin outputs.DS41615A-page 164 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150121.2 PWM Register DefinitionsREGISTER 21-1:PWMxCON: PWM CONTROL REGISTERR/W-0/0 R/W-0/0 R-0/0 R/W-0/0 U-0 U-0 U-0 U-0PWMxEN PWMxOE PWMxOUT PWMxPOL — — — —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7 PWMxEN: PWM Module Enable bit1 = PWM module is enabled0 = PWM module is disabledbit 6 PWMxOE: PWM Module Output Enable bit1 = Output to PWMx pin is enabled0 = Output to PWMx pin is disabledbit 5 PWMxOUT: PWM Module Output Value bitbit 4 PWMxPOL: PWMx Output Polarity Select bit1 = PWM output is active-low0 = PWM output is active-highbit 3-0 Unimplemented: Read as ‘0’ 2011 Microchip Technology Inc. Preliminary DS41615A-page 165

PIC12(L)F1501REGISTER 21-2:PWMxDCH: PWM DUTY CYCLE HIGH BITSR/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/uPWMxDCHbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-0PWMxDCH: PWM Duty Cycle Most Significant bitsThese bits are the MSbs of the PWM duty cycle. The two LSbs are found in the PWMxDCL register.REGISTER 21-3:PWMxDCL: PWM DUTY CYCLE LOW BITSR/W-x/u R/W-x/u U-0 U-0 U-0 U-0 U-0 U-0PWMxDCL — — — — — —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-6 PWMxDCL: PWM Duty Cycle Least Significant bitsThese bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH register.bit 5-0 Unimplemented: Read as ‘0’TABLE 21-3:SUMMARY OF REGISTERS ASSOCIATED WITH PWMName Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Registeron PagePR2 Timer2 module Period Register 157*PWM1CON PWM1EN PWM1OE PWM1OUT PWM1POL — — — — 165PWM1DCH PWM1DCH 166PWM1DCL PWM1DCL — — — — — — 166PWM2CON PWM2EN PWM2OE PWM2OUT PWM2POL — — — — 166PWM2DCH PWM2DCH 166PWM2DCL PWM2DCL — — — — — — 166PWM3CON PWM3EN PWM3OE PWM3OUT PWM3POL — — — — 165PWM3DCH PWM3DCH 166PWM3DCL PWM3DCL — — — — — — 166PWM4CON PWM4EN PWM4OE PWM4OUT PWM4POL — — — — 165PWM4DCH PWM4DCH 166PWM4DCL PWM4DCL — — — — — — 166T2CON — T2OUTPS TMR2ON T2CKPS 159TMR2 Timer2 module Register 157*TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 102Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM.* Page provides register information.Note 1: Unimplemented, read as ‘1’.DS41615A-page 166 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150122.0 CONFIGURABLE LOGIC CELL(CLC)The Configurable Logic Cell (CLC) provides programmablelogic that operates outside the speed limitationsof software execution. The logic cell takes up to 16input signals and through the use of configurable gatesreduces the 16 inputs to four logic lines that drive oneof eight selectable single-output logic functions.Input sources are a combination of the following:• I/O pins• Internal clocks• Peripherals• Register bitsThe output can be directed internally to peripherals andto an output pin.Refer to Figure 22-1 for a simplified diagram showingsignal flow through the CLCx.Possible configurations include:• Combinatorial Logic- AND- NAND- AND-OR- AND-OR-INVERT- OR-XOR- OR-XNOR• Latches- S-R- Clocked D with Set and Reset- Transparent D with Set and Reset- Clocked J-K with ResetFIGURE 22-1:CLCx SIMPLIFIED BLOCK DIAGRAMCLCxIN[0]CLCxIN[1]CLCxIN[2]CLCxIN[3]CLCxIN[4]CLCxIN[5]CLCxIN[6]CLCxIN[7]CLCxIN[8]CLCxIN[9]CLCxIN[10]CLCxIN[11]CLCxIN[12]CLCxIN[13]CLCxIN[14]CLCxIN[15]Input Data Selection Gateslcxg1lcxg2lcxg3lcxg4LCxENLogic lcxqFunctionLCxMODELCxPOLQ1lcx_outInterruptdetLCxINTPLCxINTNInterruptDLEQLCxOELCxOUTMLCxOUTTRIS ControlCLCxsetsCLCxIFflagNote: See Figure 22-2.det 2011 Microchip Technology Inc. Preliminary DS41615A-page 167

PIC12(L)F150122.1 CLCx SetupProgramming the CLCx module is performed by configuringthe 4 stages in the logic signal flow. The 4 stagesare:• Data selection• Data gating• Logic function selection• Output polarityEach stage is setup at run time by writing to the correspondingCLCx Special Function Registers. This hasthe added advantage of permitting logic reconfigurationon-the-fly during program execution.22.1.1 DATA SELECTIONThere are 16 signals available as inputs to the configurablelogic. Four 8-input multiplexers are used to selectthe inputs to pass on to the next stage. The 16 inputs tothe multiplexers are arranged in groups of four. Eachgroup is available to two of the four multiplexers, ineach case, paired with a different group. This arrangementmakes possible selection of up to two from agroup without precluding a selection from anothergroup.Data inputs are selected with the CLCxSEL0 andCLCxSEL1 registers (Register 22-3 and Register 22-4,respectively).Data inputs are selected with CLCxSEL0 andCLCxSEL1 registers (Register 22-3 and Register 22-4,respectively).Data selection is through four multiplexers as indicatedon the left side of Figure 22-2. Data inputs in the figureare identified by a generic numbered input name.Table 22-1 correlates the generic input name to theactual signal for each CLC module. The columns labeledlcxd1 through lcxd4 indicate the MUX output for theselected data input. D1S through D4S are abbreviationsfor the MUX select input codes: LCxD1S throughLCxD4S, respectively. Selecting a data input in acolumn excludes all other inputs in that column.Note:Data selections are undefined at power-up.TABLE 22-1:Data InputCLCx DATA INPUT SELECTIONlcxd1D1Slcxd2D2Slcxd3D3Slcxd4D4SCLC 1 CLC 2CLCxIN[0] 000 — — 100 CLC1IN0 CLC2IN0CLCxIN[1] 001 — — 101 CLC1IN1 CLC2IN1CLCxIN[2] 010 — — 110 sync_C1OUT sync_C1OUTCLCxIN[3] 011 — — 111 Reserved ReservedCLCxIN[4] 100 000 — — FOSC FOSCCLCxIN[5] 101 001 — — TMR0IF TMR0IFCLCxIN[6] 110 010 — — TMR1IF TMR1IFCLCxIN[7] 111 011 — — TMR2 = PR2 TMR2 = PR2CLCxIN[8] — 100 000 — lc1_out lc1_outCLCxIN[9] — 101 001 — lc2_out lc2_outCLCxIN[10] — 110 010 — Reserved ReservedCLCxIN[11] — 111 011 — Reserved ReservedCLCxIN[12] — — 100 000 NCO1OUT LFINTOSCCLCxIN[13] — — 101 001 HFINTOSC ADFRCCLCxIN[14] — — 110 010 PWM3OUT PWM1OUTCLCxIN[15] — — 111 011 PWM4OUT PWM2OUTDS41615A-page 168 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150122.1.2 DATA GATINGOutputs from the input multiplexers are directed to thedesired logic function input through the data gatingstage. Each data gate can direct any combination of thefour selected inputs.Note:Data gating is undefined at power-up.The gate stage is more than just signal direction. Thegate can be configured to direct each input signal asinverted or non-inverted data. Directed signals areANDed together in each gate. The output of each gatecan be inverted before going on to the logic functionstage.The gating is in essence a 1-to-4 inputAND/NAND/OR/NOR gate. When every input isinverted and the output is inverted, the gate is an OR ofall enabled data inputs. When the inputs and output arenot inverted, the gate is an AND or all enabled inputs.Table 22-2 summarizes the basic logic that can beobtained in gate 1 by using the gate logic select bits.The table shows the logic of four input variables, buteach gate can be configured to use less than four. Ifno inputs are selected, the output will be zero or one,depending on the gate output polarity bit.TABLE 22-2:DATA GATING LOGICCLCxGLS0 LCxG1POL Gate Logic0x55 1 AND0x55 0 NAND0xAA 1 NOR0xAA 0 OR0x00 0 Logic 00x00 1 Logic 1Data gating is indicated in the right side of Figure 22-2.Only one gate is shown in detail. The remaining threegates are configured identically with the exception thatthe data enables correspond to the enables for thatgate.22.1.3 LOGIC FUNCTIONThere are 8 available logic functions including:• AND-OR• OR-XOR• AND• S-R Latch• D Flip-Flop with Set and Reset• D Flip-Flop with Reset• J-K Flip-Flop with Reset• Transparent Latch with Set and ResetLogic functions are shown in Figure 22-3. Each logicfunction has four inputs and one output. The four inputsare the four data gate outputs of the previous stage.The output is fed to the inversion stage and from thereto other peripherals, an output pin, and back to theCLCx itself.22.1.4 OUTPUT POLARITYThe last stage in the configurable logic cell is the outputpolarity. Setting the LCxPOL bit of the CLCxCON registerinverts the output signal from the logic stage.Changing the polarity while the interrupts are enabledwill cause an interrupt for the resulting output transition.It is possible (but not recommended) to select both thetrue and negated values of an input. When this is done,the gate output is zero, regardless of the other inputs,but may emit logic glitches (transient-induced pulses).If the output of the channel must be zero or one, therecommended method is to set all gate bits to zero anduse the gate polarity bit to set the desired level.Data gating is configured with the logic gate select registersas follows:• Gate 1: CLCxGLS0 (Register 22-5)• Gate 2: CLCxGLS1 (Register 22-6)• Gate 3: CLCxGLS2 (Register 22-7)• Gate 4: CLCxGLS3 (Register 22-8)Register number suffixes are different than the gatenumbers because other variations of this module havemultiple gate selections in the same register. 2011 Microchip Technology Inc. Preliminary DS41615A-page 169

PIC12(L)F150122.1.5 CLCx SETUP STEPSThe following steps should be followed when setting upthe CLCx:• Disable CLCx by clearing the LCxEN bit.• Select desired inputs using CLCxSEL0 andCLCxSEL1 registers (See Table 22-1).• Clear any associated ANSEL bits.• Set all TRIS bits associated with inputs.• Clear all TRIS bits associated with outputs.• Enable the chosen inputs through the four gatesusing CLCxGLS0, CLCxGLS1, CLCxGLS2, andCLCxGLS3 registers.• Select the gate output polarities with theLCxPOLy bits of the CLCxPOL register.• Select the desired logic function with theLCxMODE bits of the CLCxCON register.• Select the desired polarity of the logic output withthe LCxPOL bit of the CLCxPOL register. (Thisstep may be combined with the previous gate outputpolarity step).• If driving the CLCx pin, set the LCxOE bit of theCLCxCON register and also clear the TRIS bitcorresponding to that output.• If interrupts are desired, configure the followingbits:- Set the LCxINTP bit in the CLCxCON registerfor rising event.- Set the LCxINTN bit in the CLCxCONregister or falling event.- Set the CLCxIE bit of the associated PIEregisters.- Set the GIE and PEIE bits of the INTCONregister.• Enable the CLCx by setting the LCxEN bit of theCLCxCON register.22.2 CLCx InterruptsAn interrupt will be generated upon a change in theoutput value of the CLCx when the appropriate interruptenables are set. A rising edge detector and a fallingedge detector are present in each CLC for this purpose.The CLCxIF bit of the associated PIR registers will be setwhen either edge detector is triggered and its associatedenable bit is set. The LCxINTP enables rising edge interruptsand the LCxINTN bit enables falling edge interrupts.Both are located in the CLCxCON register.To fully enable the interrupt, set the following bits:• LCxON bit of the CLCxCON register• CLCxIE bit of the associated PIE registers• LCxINTP bit of the CLCxCON register (for a risingedge detection)• LCxINTN bit of the CLCxCON register (for a fallingedge detection)• PEIE and GIE bits of the INTCON registerThe CLCxIF bit of the associated PIR registers, mustbe cleared in software as part of the interrupt service. Ifanother edge is detected while this flag is beingcleared, the flag will still be set at the end of thesequence.22.3 Output Mirror CopiesMirror copies of all LCxCON output bits are containedin the CLCxDATA register. Reading this register readsthe outputs of all CLCs simultaneously. This preventsany reading skew introduced by testing or reading theCLCxOUT bits in the individual CLCxCON registers.22.4 Effects of a ResetThe CLCxCON register is cleared to zero as the resultof a Reset. All other selection and gating values remainunchanged.22.5 Operation During SleepThe CLC module operates independently from thesystem clock and will continue to run during Sleep,provided that the input sources selected remain active.The HFINTOSC remains active during Sleep when theCLC module is enabled and the HFINTOSC isselected as an input source, regardless of the systemclock source selected.In other words, if the HFINTOSC is simultaneouslyselected as the system clock and as a CLC inputsource, when the CLC is enabled, the CPU will go idleduring Sleep, but the CLC will continue to operate andthe HFINTOSC will remain active.This will have a direct effect on the Sleep mode current.22.6 Alternate Pin LocationsThis module incorporates I/O pins that can be moved toother locations with the use of the alternate pin functionregister, APFCON. To determine which pins can bemoved and what their default locations are upon aReset, see Section 11.1 “Alternate Pin Function” formore information.DS41615A-page 170 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501FIGURE 22-2:INPUT DATA SELECTION AND GATINGCLCxIN[0]CLCxIN[1]CLCxIN[2]CLCxIN[3]CLCxIN[4]CLCxIN[5]CLCxIN[6]CLCxIN[7]000111Data Selectionlcxd1Tlcxd1NLCxD1SLCxD1G1TLCxD1G1NLCxD2G1TData GATE 1CLCxIN[4]CLCxIN[5]CLCxIN[6]CLCxIN[7]CLCxIN[8]CLCxIN[9]CLCxIN[10]CLCxIN[11]000111lcxd2Tlcxd2NLCxD2G1NLCxD3G1TLCxD3G1NLCxD4G1TLCxG1POLlcxg1LCxD2SLCxD4G1NCLCxIN[8]CLCxIN[9]CLCxIN[10]CLCxIN[11]CLCxIN[12]CLCxIN[13]CLCxIN[14]CLCxIN[15]000111LCxD3Slcxd3Tlcxd3NData GATE 2(Same as Data GATE 1)Data GATE 3(Same as Data GATE 1)lcxg2lcxg3CLCxIN[12]CLCxIN[13]CLCxIN[14]CLCxIN[15]CLCxIN[0]CLCxIN[1]CLCxIN[2]CLCxIN[3]000111lcxd4Tlcxd4N(Same as Data GATE 1)Data GATE 4lcxg4LCxD4SNote:All controls are undefined at power-up. 2011 Microchip Technology Inc. Preliminary DS41615A-page 171

PIC12(L)F1501FIGURE 22-3:PROGRAMMABLE LOGIC FUNCTIONSAND - OROR - XORlcxg1lcxg1lcxg2lcxg3lcxqlcxg2lcxg3lcxqlcxg4lcxg4LCxMODE= 000LCxMODE= 0014-Input ANDS-R Latchlcxg1lcxg2lcxg3lcxg4lcxqlcxg1lcxg2lcxg3lcxg4SRQlcxqLCxMODE= 010LCxMODE= 0111-Input D Flip-Flop with S and R2-Input D Flip-Flop with Rlcxg4lcxg2DSQlcxqlcxg4lcxg2DQlcxqlcxg1lcxg3Rlcxg1lcxg3RLCxMODE= 100LCxMODE= 101J-K Flip-Flop with R1-Input Transparent Latch with S and Rlcxg2lcxg1J Qlcxg4 KRlcxg3LCxMODE= 110lcxqlcxg4lcxg2 DSQ lcxqlcxg1 LERlcxg3LCxMODE= 111DS41615A-page 172 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150122.7 CLCx Control RegistersREGISTER 22-1:CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTERR/W-0/0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0LCxEN LCxOE LCxOUT LCxINTP LCxINTN LCxMODEbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7bit 6bit 5bit 4bit 3bit 2-0LCxEN: Configurable Logic Cell Enable bit1 = Configurable logic cell is enabled and mixing input signals0 = Configurable logic cell is disabled and has logic zero outputLCxOE: Configurable Logic Cell Output Enable bit1 = Configurable logic cell port pin output enabled0 = Configurable logic cell port pin output disabledLCxOUT: Configurable Logic Cell Data Output bitRead-only: logic cell output data, after LCxPOL; sampled from lcx_out wire.LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit1 = CLCxIF will be set when a rising edge occurs on lcx_out0 = CLCxIF will not be setLCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit1 = CLCxIF will be set when a falling edge occurs on lcx_out0 = CLCxIF will not be setLCxMODE: Configurable Logic Cell Functional Mode bits111 = Cell is 1-input transparent latch with S and R110 = Cell is J-K flip-flop with R101 = Cell is 2-input D flip-flop with R100 = Cell is 1-input D flip-flop with S and R011 = Cell is S-R latch010 = Cell is 4-input AND001 = Cell is OR-XOR000 = Cell is AND-OR 2011 Microchip Technology Inc. Preliminary DS41615A-page 173

PIC12(L)F1501REGISTER 22-2:CLCxPOL: SIGNAL POLARITY CONTROL REGISTERR/W-0/0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/uLCxPOL — — — LCxG4POL LCxG3POL LCxG2POL LCxG1POLbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7LCxPOL: LCOUT Polarity Control bit1 = The output of the logic cell is inverted0 = The output of the logic cell is not invertedbit 6-4 Unimplemented: Read as ‘0’bit 3LCxG4POL: Gate 4 Output Polarity Control bit1 = The output of gate 4 is inverted when applied to the logic cell0 = The output of gate 4 is not invertedbit 2LCxG3POL: Gate 3 Output Polarity Control bit1 = The output of gate 3 is inverted when applied to the logic cell0 = The output of gate 3 is not invertedbit 1LCxG2POL: Gate 2 Output Polarity Control bit1 = The output of gate 2 is inverted when applied to the logic cell0 = The output of gate 2 is not invertedbit 0LCxG1POL: Gate 1 Output Polarity Control bit1 = The output of gate 1 is inverted when applied to the logic cell0 = The output of gate 1 is not invertedDS41615A-page 174 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501REGISTER 22-3:CLCxSEL0: MULTIPLEXER DATA 1 AND 2 SELECT REGISTERU-0 R/W-x/u R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u— LCxD2S — LCxD1Sbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7 Unimplemented: Read as ‘0’bit 6-4 LCxD2S: Input Data 2 Selection Control bits (1)111 = CLCxIN[11] is selected for lcxd2110 = CLCxIN[10] is selected for lcxd2101 = CLCxIN[9] is selected for lcxd2100 = CLCxIN[8] is selected for lcxd2011 = CLCxIN[7] is selected for lcxd2010 = CLCxIN[6] is selected for lcxd2001 = CLCxIN[5] is selected for lcxd2000 = CLCxIN[4] is selected for lcxd2bit 3 Unimplemented: Read as ‘0’bit 2-0 LCxD1S: Input Data 1 Selection Control bits (1)111 = CLCxIN[7] is selected for lcxd1110 = CLCxIN[6] is selected for lcxd1101 = CLCxIN[5] is selected for lcxd1100 = CLCxIN[4] is selected for lcxd1011 = CLCxIN[3] is selected for lcxd1010 = CLCxIN[2] is selected for lcxd1001 = CLCxIN[1] is selected for lcxd1000 = CLCxIN[0] is selected for lcxd1Note 1:See Table 22-1 for signal names associated with inputs. 2011 Microchip Technology Inc. Preliminary DS41615A-page 175

PIC12(L)F1501REGISTER 22-4:CLCxSEL1: MULTIPLEXER DATA 3 AND 4 SELECT REGISTERU-0 R/W-x/u R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u— LCxD4S — LCxD3Sbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7 Unimplemented: Read as ‘0’bit 6-4 LCxD4S: Input Data 4 Selection Control bits (1)111 = CLCxIN[3] is selected for lcxd4110 = CLCxIN[2] is selected for lcxd4101 = CLCxIN[1] is selected for lcxd4100 = CLCxIN[0] is selected for lcxd4011 = CLCxIN[15] is selected for lcxd4010 = CLCxIN[14] is selected for lcxd4001 = CLCxIN[13] is selected for lcxd4000 = CLCxIN[12] is selected for lcxd4bit 3 Unimplemented: Read as ‘0’bit 2-0 LCxD3S: Input Data 3 Selection Control bits (1)111 = CLCxIN[15] is selected for lcxd3110 = CLCxIN[14] is selected for lcxd3101 = CLCxIN[13] is selected for lcxd3100 = CLCxIN[12] is selected for lcxd3011 = CLCxIN[11] is selected for lcxd3010 = CLCxIN[10] is selected for lcxd3001 = CLCxIN[9] is selected for lcxd3000 = CLCxIN[8] is selected for lcxd3Note 1:See Table 22-1 for signal names associated with inputs.DS41615A-page 176 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501REGISTER 22-5:CLCxGLS0: GATE 1 LOGIC SELECT REGISTERR/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/uLCxG1D4T LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T LCxG1D2N LCxG1D1T LCxG1D1Nbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0LCxG1D4T: Gate 1 Data 4 True (non-inverted) bit1 = lcxd4T is gated into lcxg10 = lcxd4T is not gated into lcxg1LCxG1D4N: Gate 1 Data 4 Negated (inverted) bit1 = lcxd4N is gated into lcxg10 = lcxd4N is not gated into lcxg1LCxG1D3T: Gate 1 Data 3 True (non-inverted) bit1 = lcxd3T is gated into lcxg10 = lcxd3T is not gated into lcxg1LCxG1D3N: Gate 1 Data 3 Negated (inverted) bit1 = lcxd3N is gated into lcxg10 = lcxd3N is not gated into lcxg1LCxG1D2T: Gate 1 Data 2 True (non-inverted) bit1 = lcxd2T is gated into lcxg10 = lcxd2T is not gated into lcxg1LCxG1D2N: Gate 1 Data 2 Negated (inverted) bit1 = lcxd2N is gated into lcxg10 = lcxd2N is not gated into lcxg1LCxG1D1T: Gate 1 Data 1 True (non-inverted) bit1 = lcxd1T is gated into lcxg10 = lcxd1T is not gated into lcxg1LCxG1D1N: Gate 1 Data 1 Negated (inverted) bit1 = lcxd1N is gated into lcxg10 = lcxd1N is not gated into lcxg1 2011 Microchip Technology Inc. Preliminary DS41615A-page 177

PIC12(L)F1501REGISTER 22-6:CLCxGLS1: GATE 2 LOGIC SELECT REGISTERR/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/uLCxG2D4T LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T LCxG2D2N LCxG2D1T LCxG2D1Nbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0LCxG2D4T: Gate 2 Data 4 True (non-inverted) bit1 = lcxd4T is gated into lcxg20 = lcxd4T is not gated into lcxg2LCxG2D4N: Gate 2 Data 4 Negated (inverted) bit1 = lcxd4N is gated into lcxg20 = lcxd4N is not gated into lcxg2LCxG2D3T: Gate 2 Data 3 True (non-inverted) bit1 = lcxd3T is gated into lcxg20 = lcxd3T is not gated into lcxg2LCxG2D3N: Gate 2 Data 3 Negated (inverted) bit1 = lcxd3N is gated into lcxg20 = lcxd3N is not gated into lcxg2LCxG2D2T: Gate 2 Data 2 True (non-inverted) bit1 = lcxd2T is gated into lcxg20 = lcxd2T is not gated into lcxg2LCxG2D2N: Gate 2 Data 2 Negated (inverted) bit1 = lcxd2N is gated into lcxg20 = lcxd2N is not gated into lcxg2LCxG2D1T: Gate 2 Data 1 True (non-inverted) bit1 = lcxd1T is gated into lcxg20 = lcxd1T is not gated into lcxg2LCxG2D1N: Gate 2 Data 1 Negated (inverted) bit1 = lcxd1N is gated into lcxg20 = lcxd1N is not gated into lcxg2DS41615A-page 178 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501REGISTER 22-7:CLCxGLS2: GATE 3 LOGIC SELECT REGISTERR/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/uLCxG3D4T LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T LCxG3D2N LCxG3D1T LCxG3D1Nbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0LCxG3D4T: Gate 3 Data 4 True (non-inverted) bit1 = lcxd4T is gated into lcxg30 = lcxd4T is not gated into lcxg3LCxG3D4N: Gate 3 Data 4 Negated (inverted) bit1 = lcxd4N is gated into lcxg30 = lcxd4N is not gated into lcxg3LCxG3D3T: Gate 3 Data 3 True (non-inverted) bit1 = lcxd3T is gated into lcxg30 = lcxd3T is not gated into lcxg3LCxG3D3N: Gate 3 Data 3 Negated (inverted) bit1 = lcxd3N is gated into lcxg30 = lcxd3N is not gated into lcxg3LCxG3D2T: Gate 3 Data 2 True (non-inverted) bit1 = lcxd2T is gated into lcxg30 = lcxd2T is not gated into lcxg3LCxG3D2N: Gate 3 Data 2 Negated (inverted) bit1 = lcxd2N is gated into lcxg30 = lcxd2N is not gated into lcxg3LCxG3D1T: Gate 3 Data 1 True (non-inverted) bit1 = lcxd1T is gated into lcxg30 = lcxd1T is not gated into lcxg3LCxG3D1N: Gate 3 Data 1 Negated (inverted) bit1 = lcxd1N is gated into lcxg30 = lcxd1N is not gated into lcxg3 2011 Microchip Technology Inc. Preliminary DS41615A-page 179

PIC12(L)F1501REGISTER 22-8:CLCxGLS3: GATE 4 LOGIC SELECT REGISTERR/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/uLCxG4D4T LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T LCxG4D2N LCxG4D1T LCxG4D1Nbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0LCxG4D4T: Gate 4 Data 4 True (non-inverted) bit1 = lcxd4T is gated into lcxg40 = lcxd4T is not gated into lcxg4LCxG4D4N: Gate 4 Data 4 Negated (inverted) bit1 = lcxd4N is gated into lcxg40 = lcxd4N is not gated into lcxg4LCxG4D3T: Gate 4 Data 3 True (non-inverted) bit1 = lcxd3T is gated into lcxg40 = lcxd3T is not gated into lcxg4LCxG4D3N: Gate 4 Data 3 Negated (inverted) bit1 = lcxd3N is gated into lcxg40 = lcxd3N is not gated into lcxg4LCxG4D2T: Gate 4 Data 2 True (non-inverted) bit1 = lcxd2T is gated into lcxg40 = lcxd2T is not gated into lcxg4LCxG4D2N: Gate 4 Data 2 Negated (inverted) bit1 = lcxd2N is gated into lcxg40 = lcxd2N is not gated into lcxg4LCxG4D1T: Gate 4 Data 1 True (non-inverted) bit1 = lcxd1T is gated into lcxg40 = lcxd1T is not gated into lcxg4LCxG4D1N: Gate 4 Data 1 Negated (inverted) bit1 = lcxd1N is gated into lcxg40 = lcxd1N is not gated into lcxg4DS41615A-page 180 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501REGISTER 22-9:CLCDATA: CLC DATA OUTPUTU-0 U-0 U-0 U-0 U-0 U-0 R-0 R-0— — — — — — MLC2OUT MLC1OUTbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-2 Unimplemented: Read as ‘0’bit 1MLC2OUT: Mirror copy of LC2OUT bitbit 0MLC1OUT: Mirror copy of LC1OUT bit 2011 Microchip Technology Inc. Preliminary DS41615A-page 181

PIC12(L)F1501TABLE 22-3:SUMMARY OF REGISTERS ASSOCIATED WITH CLCxName Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 Bit1 Bit0Registeron PageAPFCON CWG1BSEL CWG1ASEL — — T1GSEL — CLC1SEL NCO1SEL 100CLC1CON LC1EN LC1OE LC1OUT LC1INTP LC1INTN LC1MODE 173CLC2CON LC2EN LC2OE LC2OUT LC2INTP LC2INTN LC2MODE 173CLCDATA — — — — — — MLC2OUT MLC1OUT 177CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 177CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N 178CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N 179CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N 180CLC1POL LC1POL — — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL 174CLC1SEL0 — LC1D2S — LC1D1S 175CLC1SEL1 — LC1D4S — LC1D3S 176CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N 177CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N 178CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N 179CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N 180CLC2POL LC2POL — — — LC2G4POL LC2G3POL LC2G2POL LC2G1POL 174CLC2SEL0 — LC2D2S — LC2D1S 175CLC2SEL1 — LC2D4S — LC2D3S 176INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66PIE3 — — — — — — CLC2IE CLC1IE 69PIR3 — — — — — — CLC2IF CLC1IF 72TRISA — — TRISA5 TRISA4 — (1) TRISA2 TRISA1 TRISA0 102Legend: — = unimplemented read as ‘0’,. Shaded cells are not used for CLC module.Note 1: Unimplemented, read as ‘1’.DS41615A-page 182 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150123.0 NUMERICALLY CONTROLLEDOSCILLATOR (NCO) MODULEThe Numerically Controlled Oscillator (NCOx) moduleis a timer that uses the overflow from the addition of anincrement value to divide the input frequency. Theadvantage of the addition method over simple counterdriven timer is that the resolution of division does notvary with the divider value. The NCOx is most useful forapplications that require frequency accuracy and fineresolution at a fixed duty cycle.Features of the NCOx include:• 16-bit increment function• Fixed Duty Cycle (FDC) mode• Pulse Frequency (PF) mode• Output pulse width control• Multiple clock input sources• Output polarity control• Interrupt capabilityFigure 23-1 is a simplified block diagram of the NCOxmodule. 2011 Microchip Technology Inc. Preliminary DS41615A-page 183

PIC12(L)F1501FIGURE 23-1: NUMERICALLY CONTROLLED OSCILLATOR (NCOx) MODULE SIMPLIFIED BLOCK DIAGRAMIncrement16Buffer(1)16Interrupt eventNCO1CLK 1120D QLC1OUTFOSC1001HFINTOSC 00 NxEN2Accumulator20OverflowNCOx ClockQ01NxCKSNxPFMOverflowS QNxPOLRQ3NxPWSNCOx ClockRipple CounterResetNote 1: The increment registers are double-buffered to allow for value changes to be made without first disabling the NCOxmodule. They are shown here for reference. The buffers are not user-accessible.Set NCOxIF flagNCOxOUTTo CLC, CWGNxOETRIS ControlNCOxDS41615A-page 184 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150123.1 NCOx OPERATIONThe NCOx operates by repeatedly adding a fixed valueto an accumulator. Additions occur at the input clockrate. The accumulator will overflow with a carryperiodically, which is the raw NCOx output. Thiseffectively reduces the input clock by the ratio of theaddition value to the maximum accumulator value. SeeEquation 23-1.The NCOx output can be further modified by stretchingthe pulse or toggling a flip-flop. The modified NCOxoutput is then distributed internally to other peripheralsand optionally output to a pin. The accumulator overflowalso generates an interrupt.The NCOx period changes in discrete steps to create anaverage frequency. This output depends on the ability ofthe receiving circuit (i.e., CWG or external resonantconverter circuitry) to average the NCOx output toreduce uncertainty.23.1.1 NCOx CLOCK SOURCESClock sources available to the NCOx include:• HFINTOSC• FOSC• LCxOUT• CLKIN pinThe NCOx clock source is selected by configuring theNxCKS bits in the NCOxCLK register.23.1.3 ADDERThe NCOx Adder is a full adder, which operatesindependently from the system clock. The addition ofthe previous result and the increment value replacesthe accumulator value on the rising edge of each inputclock.23.1.4 INCREMENT REGISTERSThe increment value is stored in two 8-bit registersmaking up a 16-bit increment. In order of LSB to MSBthey are:• NCOxINCL• NCOxINCHBoth of the registers are readable and writeable. Theincrement registers are double-buffered to allow forvalue changes to be made without first disabling theNCOx module.The buffer loads are immediate when the module is disabled.Writing to the NCOxINCH register first is necessarybecause then the buffer is loaded synchronouslywith the NCOx operation after the write is executed onthe NCOxINCL register.Note:The increment buffer registers are notuser-accessible.23.1.2 ACCUMULATORThe accumulator is a 20-bit register. Read and writeaccess to the accumulator is available through threeregisters:• NCOxACCL• NCOxACCH• NCOxACCUEQUATION 23-1:FOVERFLOW=NCO Clock Frequency Increment Value---------------------------------------------------------------------------------------------------------------2 nn = Accumulator width in bits 2011 Microchip Technology Inc. Preliminary DS41615A-page 185

PIC12(L)F150123.2 FIXED DUTY CYCLE (FDC) MODEIn Fixed Duty Cycle (FDC) mode, every time theaccumulator overflows, the output is toggled. Thisprovides a 50% duty cycle, provided that the incrementvalue remains constant. For more information, seeFigure 23-2.The FDC mode is selected by clearing the NxPFM bitin the NCOxCON register.23.3 PULSE FREQUENCY (PF) MODEIn Pulse Frequency (PF) mode, every time the accumulatoroverflows, the output becomes active for one ormore clock periods. Once the clock period expires, theoutput returns to an inactive state. This provides apulsed output.The output becomes active on the rising clock edgeimmediately following the overflow event. For moreinformation, see Figure 23-2.The value of the active and inactive states depends onthe polarity bit, NxPOL in the NCOxCON register.The PF mode is selected by setting the NxPFM bit inthe NCOxCON register.23.3.1 OUTPUT PULSE WIDTH CONTROLWhen operating in PF mode, the active state of the outputcan vary in width by multiple clock periods. Variouspulse widths are selected with the NxPWS bits inthe NCOxCLK register.When the selected pulse width is greater than theaccumulator overflow time frame, the output of theNCOx operation is indeterminate.23.4 OUTPUT POLARITY CONTROLThe last stage in the NCOx module is the output polarity.The NxPOL bit in the NCOxCON register selects theoutput polarity. Changing the polarity while the interruptsare enabled will cause an interrupt for the resultingoutput transition.The NCOx output can be used internally by sourcecode or other peripherals. Accomplish this by readingthe NxOUT (read-only) bit of the NCOxCON register.DS41615A-page 186 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501FIGURE 23-2: FDC OUTPUT MODE OPERATION DIAGRAMClock SourceNCOxIncrementValue2000hNCOxAccumulatorInput02000h 04000h 06000h 08000h 0A000h 0C000h 0E000h 10000h 02000h 04000h 06000h 08000h 0A000h 0C000h 0E000h 10000h 02000h 04000hTadderAccumulator Input OverflowOverflow is theMSB of the accumulatorTadder_NCOx 0000h 2000h 4000h 6000h 8000h A000h C000h E000h 0000h 2000h 4000h 6000h 8000h A000h C000h E000h 0000h 2000hAccumulatorValueTadderTadderOverflowPWS = 000InterruptEventNCOx OutputFDC modeNCOx Output PF modeNCOX PWS = 000NCOx Output PF modeNCOx PWS = 010DS41615A-page 187 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150123.5 InterruptsWhen the accumulator overflows, the NCOx InterruptFlag bit, NCOxIF, of the PIRx register is set. To enablethe interrupt event, the following bits must be set:• NxEN bit of the NCOxCON register• NCOxIE bit of the PIEx register• PEIE bit of the INTCON register• GIE bit of the INTCON registerThe interrupt must be cleared by software by clearingthe NCOxIF bit in the Interrupt Service Routine.23.6 Effects of a ResetAll of the NCOx registers are cleared to zero as theresult of a Reset.23.7 Operation In SleepThe NCO module operates independently from thesystem clock and will continue to run during Sleep,provided that the clock source selected remainsactive.The HFINTOSC remains active during Sleep when theNCO module is enabled and the HFINTOSC isselected as the clock source, regardless of the systemclock source selected.In other words, if the HFINTOSC is simultaneouslyselected as the system clock and the NCO clocksource, when the NCO is enabled, the CPU will go idleduring Sleep, but the NCO will continue to operate andthe HFINTOSC will remain active.This will have a direct effect on the Sleep mode current.23.8 Alternate Pin LocationsThis module incorporates I/O pins that can be moved toother locations with the use of the alternate pin functionregister, APFCON. To determine which pins can bemoved and what their default locations are upon aReset, see Section 11.1 “Alternate Pin Function” formore information.DS41615A-page 188 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150123.9 NCOx Control RegistersREGISTER 23-1:NCOxCON: NCOx CONTROL REGISTERR/W-0/0 R/W-0/0 R-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0NxEN NxOE NxOUT NxPOL — — — NxPFMbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7NxEN: NCOx Enable bit1 = NCOx module is enabled0 = NCOx module is disabledbit 6NxOE: NCOx Output Enable bit1 = NCOx output pin is enabled0 = NCOx output pin is disabledbit 5NxOUT: NCOx Output bit1 = NCOx output is high0 = NCOx output is lowbit 4NxPOL: NCOx Polarity bit1 = NCOx output signal is active-high0 = NCOx output signal is active-lowbit 3-1 Unimplemented: Read as ‘0’.bit 0NxPFM: NCOx Pulse Frequency Mode bit1 = NCOx operates in Pulse Frequency mode0 = NCOx operates in Fixed Duty Cycle modeREGISTER 23-2:NCOxCLK: NCOx INPUT CLOCK CONTROL REGISTERR/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0NxPWS — — — NxCKSbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is cleared(1, 2)bit 7-5 NxPWS: NCOx Output Pulse Width Select bits111 = 128 NCOx clock periods110 = 64 NCOx clock periods101 = 32 NCOx clock periods100 = 16 NCOx clock periods011 = 8 NCOx clock periods010 = 4 NCOx clock periods001 = 2 NCOx clock periods000 = 1 NCOx clock periodsbit 4-2 Unimplemented: Read as ‘0’bit 1-0 NxCKS: NCOx Clock Source Select bits11 = NCO1CLK10 = LC1OUT01 = FOSC00 = HFINTOSC (16 MHz)Note 1: NxPWS applies only when operating in Pulse Frequency mode.2: If NCOx pulse width is greater than NCOx overflow period, operation is undeterminate. 2011 Microchip Technology Inc. Preliminary DS41615A-page 189

PIC12(L)F1501REGISTER 23-3: NCOxACCL: NCOx ACCUMULATOR REGISTER – LOW BYTER/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0NCOxACCbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-0NCOxACC: NCOx Accumulator, low byteREGISTER 23-4: NCOxACCH: NCOx ACCUMULATOR REGISTER – HIGH BYTER/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0NCOxACCbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-0NCOxACC: NCOx Accumulator, high byteREGISTER 23-5: NCOxACCU: NCOx ACCUMULATOR REGISTER – UPPER BYTEU-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0— — — — NCOxACCbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-4 Unimplemented: Read as ‘0’bit 3-0NCOxACC: NCOx Accumulator, upper byteDS41615A-page 190 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501REGISTER 23-6: NCOxINCL: NCOx INCREMENT REGISTER – LOW BYTER/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1NCOxINCbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-0NCOxINC: NCOx Increment, low byteREGISTER 23-7: NCOxINCH: NCOx INCREMENT REGISTER – HIGH BYTER/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0NCOxINCbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is clearedbit 7-0NCOxINC: NCOx Increment, high byte 2011 Microchip Technology Inc. Preliminary DS41615A-page 191

PIC12(L)F1501TABLE 23-1:SUMMARY OF REGISTERS ASSOCIATED WITH NCOxName Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Registeron PageAPFCON CWG1BSEL CWG1ASEL — — T1GSEL — CLC1SEL NCO1SEL 100INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 66NCO1ACCH NCO1ACC 190NCO1ACCL NCO1ACC 190NCO1ACCU — NCO1ACC 190NCO1CLK N1PWS — — — N1CKS 189NCO1CON N1EN N1OE N1OUT N1POL — — — N1PFM 189NCO1INCH NCO1INC 191NCO1INCL NCO1INC 191PIE2 — — C1IE — — NCO1IE — — 68PIR2 — — C1IF — — NCO1IF — — 71TRISA — — TRISA5 TRISA4 — (1) TRISA2 TRISA1 TRISA0 102Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are notused for ADC module.Note 1: Unimplemented, read as ‘1’.DS41615A-page 192 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150124.0 COMPLEMENTARY WAVEFORMGENERATOR (CWG) MODULEThe Complementary Waveform Generator (CWG) producesa complementary waveform with dead-banddelay from a selection of input sources.The CWG module has the following features:• Selectable dead-band clock source control• Selectable input sources• Output enable control• Output polarity control• Dead-band control with independent 6-bit risingand falling edge dead-band counters• Auto-shutdown control with:- Selectable shutdown sources- Auto-restart enable- Auto-shutdown pin override control 2011 Microchip Technology Inc. Preliminary DS41615A-page 193

PIC12(L)F1501FIGURE 24-1: SIMPLIFIED CWG BLOCK DIAGRAMGxCS1FOSCcwg_clock1HFINTOSCGxISasync_C1OUTReservedPWM1OUTPWM2OUTPWM3OUTPWM4OUTNCO1OUTLC1OUT3Input SourceCWG1FLT (INT pin)GxASDFLTasync_C1OUTGxASDC1LC2OUTGxASCLCAuto-ShutdownSourceSQR QWRITEGxASE Data BitGxARSENset dominatex = CWG module numberSQR QD SQCWGxDBR6ENRCWGxDBF6ENRGxASEshutdown==GxASDLA‘0’‘1’GxPOLAGxPOLB‘0’‘1’GxASDLB20010110010112GxASDLA = 011001GxASDLB = 01TRISxTRISxGxOEACWGxAGxOEBCWGxB 2011 Microchip Technology Inc. Preliminary DS41615A-page 194

PIC12(L)F1501FIGURE 24-2:TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN)cwg_clockPWM1CWGxACWGxBRising EdgeDead BandRising Edge Dead BandRising Edge DFalling Edge Dead BandFalling Edge Dead Band 2011 Microchip Technology Inc. Preliminary DS41615A-page 195

PIC12(L)F150124.1 Fundamental OperationThe CWG generates a two output complementarywaveform from one of four selectable input sources.The off-to-on transition of each output can be delayedfrom the on-to-off transition of the other output, thereby,creating a time delay immediately where neither outputis driven. This is referred to as dead time and is coveredin Section 24.5 “Dead-Band Control”. A typicaloperating waveform, with dead band, generated from asingle input signal is shown in Figure 24-2.It may be necessary to guard against the possibility ofcircuit faults or a feedback event arriving too late or notat all. In this case, the active drive must be terminatedbefore the Fault condition causes damage. This isreferred to as auto-shutdown and is covered inSection 24.9 “Auto-shutdown Control”.24.2 Clock SourceThe CWG module allows the following clock sourcesto be selected:• Fosc (system clock)• HFINTOSC (16 MHz only)The clock sources are selected using the G1CS0 bit ofthe CWGxCON0 register (Register 24-1).24.3 Selectable Input SourcesThe CWG can generate the complementary waveformfor the following input sources:• async_C1OUT• PWM1• PWM2• PWM3• PWM4• N1OUT• LC1OUTThe input sources are selected using the GxISbits in the CWGxCON1 register (Register 24-2).24.4 Output ControlImmediately after the CWG module is enabled, thecomplementary drive is configured with both CWGxAand CWGxB drives cleared.24.4.2 POLARITY CONTROLThe polarity of each CWG output can be selectedindependently. When the output polarity bit is set, thecorresponding output is active high. Clearing the outputpolarity bit configures the corresponding output asactive low. However, polarity does not affect theoverride levels. Output polarity is selected with theGxPOLA and GxPOLB bits of the CWGxCON0 register.24.5 Dead-Band ControlDead-band control provides for non-overlapping outputsignals to prevent shoot-through current in powerswitches. The CWG contains two 6-bit dead-bandcounters. One dead-band counter is used for the risingedge of the input source control. The other is used forthe falling edge of the input source control.Dead band is timed by counting CWG clock periodsfrom zero up to the value in the rising or falling deadbandcounter registers. See CWGxDBR andCWGxDBF registers (Register 24-4 and Register 24-5,respectively).24.6 Rising Edge Dead BandThe rising edge dead band delays the turn-on of theCWGxA output from when the CWGxB output is turnedoff. The rising edge dead-band time starts when therising edge of the input source signal goes true. Whenthis happens, the CWGxB output is immediately turnedoff and the rising edge dead-band delay time starts.When the rising edge dead-band delay time is reached,the CWGxA output is turned on.The CWGxDBR register sets the duration of the deadbandinterval on the rising edge of the input sourcesignal. This duration is from 0 to 64 counts of dead band.Dead band is always counted off the edge on the inputsource signal. A count of 0 (zero) indicates that nodead band is present.If the input source signal is not present for enough timefor the count to be completed, no output will be seen onthe respective output.24.4.1 OUTPUT ENABLESEach CWG output pin has individual output enablecontrol. Output enables are selected with the GxOEAand GxOEB bits of the CWGxCON0 register. When anoutput enable control is cleared, the module asserts nocontrol over the pin. When an output enable is set, theoverride value or active PWM waveform is applied tothe pin per the port priority selection. The output pinenables are dependent on the module enable bit,GxEN. When GxEN is cleared, CWG output enablesand CWG drive levels have no effect.DS41615A-page 196 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150124.7 Falling Edge Dead BandThe falling edge dead band delays the turn-on of theCWGxB output from when the CWGxA output is turnedoff. The falling edge dead-band time starts when thefalling edge of the input source goes true. When thishappens, the CWGxA output is immediately turned offand the falling edge dead-band delay time starts. Whenthe falling edge dead-band delay time is reached, theCWGxB output is turned on.The CWGxDBF register sets the duration of the deadbandinterval on the falling edge of the input source signal.This duration is from 0 to 64 counts of dead band.Dead band is always counted off the edge on the inputsource signal. A count of 0 (zero) indicates that nodead band is present.If the input source signal is not present for enough timefor the count to be completed, no output will be seen onthe respective output.Refer to Figure 24-3 and Figure 24-4 for examples.24.8 Dead-Band UncertaintyWhen the rising and falling edges of the input sourcetriggers the dead-band counters, the input may be asynchronous.This will create some uncertainty in the deadbandtime delay. The maximum uncertainty is equal toone CWG clock period. Refer to Equation 24-1 for moredetail. 2011 Microchip Technology Inc. Preliminary DS41615A-page 197

PIC12(L)F1501FIGURE 24-3: DEAD-BAND OPERATION, CWGxDBR = 01H, CWGxDBF = 02Hcwg_clockInput SourceCWGxACWGxBFIGURE 24-4: DEAD-BAND OPERATION, CWGxDBR = 03H, CWGxDBF = 04H, SOURCE SHORTER THAN DEAD BANDcwg_clockInput SourceCWGxACWGxBsource shorter than dead band 2011 Microchip Technology Inc. Preliminary DS41615A-page 198

PIC12(L)F1501EQUATION 24-1:DEAD-BANDUNCERTAINTYTDEADBAND_UNCERTAINTY=1----------------------------Fcwg_clockExample:Fcwg_clock=16 MHzTherefore:TDEADBAND_UNCERTAINTY=1----------------------------Fcwg_clock==1------------------16 MHz625ns 2011 Microchip Technology Inc. Preliminary DS41615A-page 199

PIC12(L)F150124.9 Auto-shutdown ControlAuto-shutdown is a method to immediately override theCWG output levels with specific overrides that allow forsafe shutdown of the circuit. The shutdown state can beeither cleared automatically or held until cleared bysoftware.24.9.1 SHUTDOWNThe shutdown state can be entered by either of the followingtwo methods:• Software generated• External Input24.9.1.1 Software Generated ShutdownSetting the GxASE bit of the CWGxCON2 register willforce the CWG into the shutdown state.When auto-restart is disabled, the shutdown state willpersist as long as the GxASE bit is set.When auto-restart is enabled, the GxASE bit will clearautomatically and resume operation on the next risingedge event. See Figure 24-6.24.9.1.2 External Input SourceExternal shutdown inputs provide the fastest way tosafely suspend CWG operation in the event of a Faultcondition. When any of the selected shutdown inputsgoes active, the CWG outputs will immediately go tothe selected override levels without software delay. Anycombination of two input sources can be selected tocause a shutdown condition. The sources are:• async_C1OUT• LC2OUT• CWG1FLTShutdown inputs are selected using the GxASDS0 andGxASDS1 bits of the CWGxCON2 register.(Register 24-3).Note:Shutdown inputs are level sensitive, notedge sensitive. The shutdown state cannotbe cleared, except by disabling autoshutdown,as long as the shutdown inputlevel persists.24.10 Operation During SleepThe CWG module operates independently from thesystem clock and will continue to run during Sleep,provided that the clock and input sources selectedremain active.The HFINTOSC remains active during Sleep, providedthat the CWG module is enabled, the input source isactive, and the HFINTOSC is selected as the clocksource, regardless of the system clock sourceselected.In other words, if the HFINTOSC is simultaneouslyselected as the system clock and the CWG clocksource, when the CWG is enabled and the inputsource is active, the CPU will go idle during Sleep, butthe CWG will continue to operate and the HFINTOSCwill remain active.This will have a direct effect on the Sleep mode current.24.11 Alternate Pin LocationsThis module incorporates I/O pins that can be moved toother locations with the use of the alternate pin functionregister, APFCON. To determine which pins can bemoved and what their default locations are upon aReset, see Section 11.1 “Alternate Pin Function” formore information.DS41615A-page 200 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150124.12 Configuring the CWGThe following steps illustrate how to properly configurethe CWG to ensure a synchronous start:1. Ensure that the TRIS control bits correspondingto CWGxA and CWGxB are set so that both areconfigured as inputs.2. Clear the GxEN bit, if not already cleared.3. Set desired dead-band times with the CWGxDBRand CWGxDBF registers.4. Setup the following controls in CWGxCON2auto-shutdown register:• Select desired shutdown source.• Select both output overrides to the desiredlevels (this is necessary even if not usingauto-shutdown because start-up will be froma shutdown state).• Set the GxASE bit and clear the GxARSENbit.5. Select the desired input source using theCWGxCON1 register.6. Configure the following controls in CWGxCON0register:• Select desired clock source.• Select the desired output polarities.• Set the output enables for the outputs to beused.7. Set the GxEN bit.8. Clear TRIS control bits corresponding toCWGxA and CWGxB to be used to configurethose pins as outputs.9. If auto-restart is to be used, set the GxARSENbit and the GxASE bit will be cleared automatically.Otherwise, clear the GxASE bit to start theCWG.24.12.1 PIN OVERRIDE LEVELSThe levels driven to the output pins, while the shutdowninput is true, are controlled by the GxASDLA andGxASDLB bits of the CWGxCON2 register(Register 24-3). GxASDLA controls the CWG1Aoverride level and GxASDLB controls the CWG1Boverride level. The control bit logic level corresponds tothe output logic drive level while in the shutdown state.The polarity control does not apply to the override level.24.12.2 AUTO-SHUTDOWN RESTARTAfter an auto-shutdown event has occurred, there aretwo ways to have resume operation:• Software controlled• Auto-restartThe restart method is selected with the GxARSEN bitof the CWGxCON2 register. Waveforms of softwarecontrolled and automatic restarts are shown inFigure 24-5 and Figure 24-6.24.12.2.1 Software Controlled RestartWhen the GxARSEN bit of the CWGxCON2 register iscleared, the CWG must be restarted after an auto-shutdownevent by software.Clearing the shutdown state requires all selected shutdowninputs to be low, otherwise the GxASE bit willremain set. The overrides will remain in effect until thefirst rising edge event after the GxASE bit is cleared.The CWG will then resume operation.24.12.2.2 Auto-RestartWhen the GxARSEN bit of the CWGxCON2 register isset, the CWG will restart from the auto-shutdown stateautomatically.The GxASE bit will clear automatically when all shutdownsources go low. The overrides will remain ineffect until the first rising edge event after the GxASEbit is cleared. The CWG will then resume operation. 2011 Microchip Technology Inc. Preliminary DS41615A-page 201

PIC12(L)F1501FIGURE 24-5: SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (GxARSEN = 0,GxASDLA = 01, GxASDLB = 01)Shutdown Event CeasesGxASE Cleared by SoftwareCWG InputSourceShutdown SourceGxASECWG1ATri-State (No Pulse)CWG1B Tri-State (No Pulse)No ShutdownShutdownOutput ResumesFIGURE 24-6: SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (GxARSEN = 1,GxASDLA = 01, GxASDLB = 01)Shutdown Event CeasesGxASE auto-cleared by hardwareCWG InputSourceShutdown SourceGxASECWG1ATri-State (No Pulse)CWG1BTri-State (No Pulse)No ShutdownShutdownOutput Resumes 2011 Microchip Technology Inc. Preliminary DS41615A-page 202

PIC12(L)F150124.13 CWG Control RegistersREGISTER 24-1: CWGxCON0: CWG CONTROL REGISTER 0R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0GxEN GxOEB GxOEA GxPOLB GxPOLA — — GxCS0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on conditionbit 7GxEN: CWGx Enable bit1 = Module is enabled0 = Module is disabledbit 6GxOEB: CWGxB Output Enable bit1 = CWGxB is available on appropriate I/O pin0 = CWGxB is not available on appropriate I/O pinbit 5GxOEA: CWGxA Output Enable bit1 = CWGxA is available on appropriate I/O pin0 = CWGxA is not available on appropriate I/O pinbit 4GxPOLB: CWGxB Output Polarity bit1 = Output is inverted polarity0 = Output is normal polaritybit 3GxPOLA: CWGxA Output Polarity bit1 = Output is inverted polarity0 = Output is normal polaritybit 2-1 Unimplemented: Read as ‘0’bit 0GxCS0: CWGx Clock Source bit1 = HFINTOSC0 = FOSC 2011 Microchip Technology Inc. Preliminary DS41615A-page 203

PIC12(L)F1501REGISTER 24-2: CWGxCON1: CWG CONTROL REGISTER 1R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 R/W-0/0 R/W-0/0 R/W-0/0GxASDLB GxASDLA — GxISbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on conditionbit 7-6 GxASDLB: CWGx Shutdown State for CWGxBWhen an auto shutdown event is present (GxASE = 1):11 = CWGxB pin is driven to ‘1’, regardless of the setting of the GxPOLB bit.10 = CWGxB pin is driven to ‘0’, regardless of the setting of the GxPOLB bit.01 = CWGxB pin is tri-stated00 = CWGxB pin is driven to it’s inactive state after the selected dead-band interval. GxPOLB still willcontrol the polarity of the output.bit 5-4 GxASDLA: CWGx Shutdown State for CWGxAWhen an auto shutdown event is present (GxASE = 1):11 = CWGxA pin is driven to ‘1’, regardless of the setting of the GxPOLA bit.10 = CWGxA pin is driven to ‘0’, regardless of the setting of the GxPOLA bit.01 = CWGxA pin is tri-stated00 = CWGxA pin is driven to it’s inactive state after the selected dead-band interval. GxPOLA still willcontrol the polarity of the output.bit 3 Unimplemented: Read as ‘0’bit 2-0 GxIS: CWGx Input Source Select bits111 = LC1OUT110 = N1OUT101 = PWM4OUT100 = PWM3OUT011 = PWM2OUT010 = PWM1OUT001 = async_C1OUT000 = ReservedDS41615A-page 204 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501REGISTER 24-3: CWGxCON2: CWG CONTROL REGISTER 2R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0G1ASE G1ARSEN — — — G1ASDC1 G1ASDFLT G1ASDCLC2bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on conditionbit 7G1ASE: Auto-Shutdown Event Status bit1 = An auto-shutdown event has occurred0 = No auto-shutdown event has occurredbit 6G1ARSEN: Auto-Restart Enable bit1 = Auto-restart is enabled0 = Auto-restart is disabledbit 5-3 Unimplemented: Read as ‘0’bit 2G1ASDC1: CWG Auto-shutdown on Comparator 1 Enable bit1 = Shutdown when Comparator 1 output is high0 = Comparator 1 output has no effect on shutdownbit 1G1ASDFLT: CWG Auto-shutdown on FLT Enable bit1 = Shutdown when CWG1FLT in put is low0 = CWG1FLT input has no effect on shutdownbit 0G1ASDCLC2: CWG Auto-shutdown on CLC2 Enable bit1 = Shutdown when LC2OUT is high0 = LC2OUT has no effect on shutdown 2011 Microchip Technology Inc. Preliminary DS41615A-page 205

PIC12(L)F1501REGISTER 24-4: CWGxDBR: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) RISINGDEAD-BAND COUNT REGISTERU-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u— — CWGxDBRbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on conditionbit 7-6 Unimplemented: Read as ‘0’bit 5-0 CWGxDBR: Complementary Waveform Generator (CWGx) Rising counts11 1111 = 63-64 counts of dead band11 1110 = 62-63 counts of dead bandREGISTER 24-5:00 0010 = 2-3 counts of dead band00 0001 = 1-2 counts of dead band00 0000 = 0 counts of dead bandCWGxDBF: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) FALLINGDEAD-BAND COUNT REGISTERU-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u— — CWGxDBFbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on conditionbit 7-6 Unimplemented: Read as ‘0’bit 5-0 CWGxDBF: Complementary Waveform Generator (CWGx) Falling counts11 1111 = 63-64 counts of dead band11 1110 = 62-63 counts of dead band00 0010 = 2-3 counts of dead band00 0001 = 1-2 counts of dead band00 0000 = 0 counts of dead band. Dead-band generation is bypassed.DS41615A-page 206 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150124.13.1 ALTERNATE PIN LOCATIONSThis module incorporates I/O pins that can be moved toother locations with the use of the alternate pin functionregister, APFCON. To determine which pins can bemoved and what their default locations are upon aReset, see Section 11.1 “Alternate Pin Function” formore information.TABLE 24-1:SUMMARY OF REGISTERS ASSOCIATED WITH CWGName Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Registeron PageANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 103APFCON CWG1BSEL CWG1ASEL — — T1GSEL — CLC1SEL NCO1SEL 100CWG1CON0 G1EN G1OEB G1OEA G1POLB G1POLA — — G1CS0 203CWG1CON1 G1ASDLB G1ASDLA — — G1IS 204CWG1CON2 G1ASE G1ARSEN — — — G1ASDC1 G1ASDFLT G1ASDCLC2 205CWG1DBF — — CWG1DBF 206CWG1DBR — — CWG1DBR 206TRISA — — TRISA5 TRISA4 — (1) TRISA2 TRISA1 TRISA0 102Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by CWG.Note 1: Unimplemented, read as ‘1’. 2011 Microchip Technology Inc. Preliminary DS41615A-page 207

PIC12(L)F1501NOTES:DS41615A-page 208 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150125.0 IN-CIRCUIT SERIALPROGRAMMING (ICSP)ICSP programming allows customers to manufacturecircuit boards with unprogrammed devices. Programmingcan be done after the assembly process, allowing thedevice to be programmed with the most recent firmwareor a custom firmware. Five pins are needed for ICSPprogramming:• ICSPCLK• ICSPDAT• MCLR/VPP• VDD• VSSIn Program/Verify mode the program memory, user IDsand the Configuration Words are programmed throughserial communications. The ICSPDAT pin is a bidirectionalI/O used for transferring the serial data and theICSPCLK pin is the clock input. For more information onICSP refer to the “PIC16193X/PIC16LF193X MemoryProgramming Specification” (DS41360).25.1 High-Voltage Programming EntryModeThe device is placed into High-Voltage ProgrammingEntry mode by holding the ICSPCLK and ICSPDATpins low then raising the voltage on MCLR/VPP to VIHH.25.2 Low-Voltage Programming EntryModeThe Low-Voltage Programming Entry mode allows thePIC ® Flash MCUs to be programmed using VDD only,without high voltage. When the LVP bit of ConfigurationWords is set to ‘1’, the low-voltage ICSP programmingentry is enabled. To disable the Low-Voltage ICSPmode, the LVP bit must be programmed to ‘0’.Entry into the Low-Voltage Programming Entry moderequires the following steps:1. MCLR is brought to VIL.2. A 32-bit key sequence is presented onICSPDAT, while clocking ICSPCLK.Once the key sequence is complete, MCLR must beheld at VIL for as long as Program/Verify mode is to bemaintained.If low-voltage programming is enabled (LVP = 1), theMCLR Reset function is automatically enabled andcannot be disabled. See Section MCLR for more information.The LVP bit can only be reprogrammed to ‘0’ by usingthe High-Voltage Programming mode.25.3 Common Programming InterfacesConnection to a target device is typically done throughan ICSP header. A commonly found connector ondevelopment tools is the RJ-11 in the 6P6C (6 pin, 6connector) configuration. See Figure 25-1.FIGURE 25-1:VDDVPP/MCLRICD RJ-11 STYLECONNECTOR INTERFACEICSPDAT2 4 6 NCICSPCLK1 3 5VSSPin Description*1 = VPP/MCLR2 = VDD Target3 = VSS (ground)4 = ICSPDAT5 = ICSPCLK6 = No ConnectTargetPC BoardBottom SideAnother connector often found in use with the PICkitprogrammers is a standard 6-pin header with 0.1 inchspacing. Refer to Figure 25-2. 2011 Microchip Technology Inc. Preliminary DS41615A-page 209

PIC12(L)F1501FIGURE 25-2:PICkit PROGRAMMER STYLE CONNECTOR INTERFACEPin 1 Indicator123456Pin Description*1 = VPP/MCLR2 = VDD Target3 = VSS (ground)4 = ICSPDAT5 = ICSPCLK6 = No Connect* The 6-pin header (0.100" spacing) accepts 0.025" square pins.For additional interface recommendations, refer to yourspecific device programmer manual prior to PCBdesign.It is recommended that isolation devices be used toseparate the programming pins from other circuitry.The type of isolation is highly dependent on the specificapplication and may include devices such as resistors,diodes, or even jumpers. See Figure 25-3 for moreinformation.FIGURE 25-3:TYPICAL CONNECTION FOR ICSP PROGRAMMINGExternalProgrammingSignalsVDDVDDDevice to beProgrammedVDDVPPVSSMCLR/VPPVSSDataClockICSPDATICSPCLK* * *To Normal Connections*Isolation devices (as required).DS41615A-page 210 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150126.0 INSTRUCTION SET SUMMARYEach instruction is a 14-bit word containing the operationcode (opcode) and all required operands. The opcodes are broken into three broad categories.• Byte Oriented• Bit Oriented• Literal and ControlThe literal and control category contains the most variedinstruction word format.Table 26-3 lists the instructions recognized by theMPASM TM assembler.All instructions are executed within a single instructioncycle, with the following exceptions, which may taketwo or three cycles:• Subroutine takes two cycles (CALL, CALLW)• Returns from interrupts or subroutines take twocycles (RETURN, RETLW, RETFIE)• Program branching takes two cycles (GOTO, BRA,BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)• One additional instruction cycle will be used whenany instruction references an indirect file registerand the file select register is pointing to programmemory.One instruction cycle consists of 4 oscillator cycles; foran oscillator frequency of 4 MHz, this gives a nominalinstruction execution rate of 1 MHz.All instruction examples use the format ‘0xhh’ torepresent a hexadecimal number, where ‘h’ signifies ahexadecimal digit.26.1 Read-Modify-Write OperationsAny instruction that specifies a file register as part ofthe instruction performs a Read-Modify-Write (R-M-W)operation. The register is read, the data is modified,and the result is stored according to either the instruction,or the destination designator ‘d’. A read operationis performed on a register even if the instruction writesto that register.TABLE 26-1:FieldTABLE 26-2:OPCODE FIELDDESCRIPTIONSDescriptionf Register file address (0x00 to 0x7F)W Working register (accumulator)b Bit address within an 8-bit file registerk Literal field, constant data or labelx Don’t care location (= 0 or 1).The assembler will generate code with x = 0.It is the recommended form of use forcompatibility with all Microchip software tools.d Destination select; d = 0: store result in W,d = 1: store result in file register f.Default is d = 1.n FSR or INDF number. (0-1)mmFieldPCTOCDCZPDPre-post increment-decrement modeselectionProgram CounterTime-out bitCarry bitDigit carry bitZero bitPower-down bitABBREVIATIONDESCRIPTIONSDescription 2011 Microchip Technology Inc. Preliminary DS41615A-page 211

PIC12(L)F1501FIGURE 26-1:GENERAL FORMAT FORINSTRUCTIONSByte-oriented file register operations13 8 7 6 0OPCODE d f (FILE #)d = 0 for destination Wd = 1 for destination ff = 7-bit file register addressBit-oriented file register operations13 10 9 7 6 0OPCODE b (BIT #) f (FILE #)b = 3-bit bit addressf = 7-bit file register addressLiteral and control operationsGeneral13 8 7 0OPCODEk (literal)k = 8-bit immediate valueCALL and GOTO instructions only13 11 10 0OPCODEk (literal)k = 11-bit immediate valueMOVLP instruction only13 7 6 0OPCODEk (literal)k = 7-bit immediate valueMOVLB instruction only13 5 4 0OPCODEk (literal)k = 5-bit immediate valueBRA instruction only13 9 8 0OPCODEk (literal)k = 9-bit immediate valueFSR Offset instructions13 7 6 5 0OPCODE n k (literal)n = appropriate FSRk = 6-bit immediate valueFSR Increment instructions13 3 2 1 0OPCODEn m (mode)n = appropriate FSRm = 2-bit mode valueOPCODE only13 0OPCODEDS41615A-page 212 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501TABLE 26-3:PIC12(L)F1501 ENHANCED INSTRUCTION SETMnemonic,OperandsDescriptionCyclesMSb14-Bit OpcodeLSbStatusAffectedNotesBYTE-ORIENTED FILE REGISTER OPERATIONSADDWFADDWFCANDWFASRFLSLFLSRFCLRFCLRWCOMFDECFINCFIORWFMOVFMOVWFRLFRRFSUBWFSUBWFBSWAPFXORWFf, df, df, df, df, df, df–f, df, df, df, df, dff, df, df, df, df, df, dAdd W and fAdd with Carry W and fAND W with fArithmetic Right ShiftLogical Left ShiftLogical Right ShiftClear fClear WComplement fDecrement fIncrement fInclusive OR W with fMove fMove W to fRotate Left f through CarryRotate Right f through CarrySubtract W from fSubtract with Borrow W from fSwap nibbles in fExclusive OR W with f11111111111111111111001100111111000000000000000000000011000001111101010101110101011000010001100100111010010010000000110111000010101111100110dfffdfffdfffdfffdfffdffflfff0000dfffdfffdfffdfffdfff1fffdfffdfffdfffdfffdfffdfffffffffffffffffffffffffffffff00xxffffffffffffffffffffffffffffffffffffffffffffffffC, DC, ZC, DC, ZZC, ZC, ZC, ZZZZZZZZCCC, DC, ZC, DC, ZZ2222222222222222222BYTE ORIENTED SKIP OPERATIONSDECFSZINCFSZf, df, dDecrement f, Skip if 0Increment f, Skip if 01(2)1(2)000010111111dfffdfffffffffff1, 21, 2BIT-ORIENTED FILE REGISTER OPERATIONSBCFBSFf, bf, bBit Clear fBit Set f11010100bb01bbbfffbfffffffffff22BTFSCBTFSSf, bf, bLITERAL OPERATIONSADDLWANDLWIORLWMOVLBMOVLPMOVLWSUBLWXORLWkkkkkkkkBit Test f, Skip if ClearBit Test f, Skip if SetAdd literal and WAND literal with WInclusive OR literal with WMove literal to BSRMove literal to PCLATHMove literal to WSubtract W from literalExclusive OR literal with WBIT-ORIENTED SKIP OPERATIONS1 (2)1 (2)111111110101111111001111111110bb11bb11101001100000000001000011001010bfffbfffkkkkkkkkkkkk001k1kkkkkkkkkkkkkkkffffffffkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkC, DC, ZZZC, DC, ZZNote 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycleis executed as a NOP.2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require oneadditional instruction cycle.1, 21, 2 2011 Microchip Technology Inc. Preliminary DS41615A-page 213

PIC12(L)F1501TABLE 26-3:BRABRWCALLCALLWGOTORETFIERETLWRETURNCLRWDTNOPOPTIONRESETSLEEPTRISADDFSRMOVIWMOVWIMnemonic,Operandsk–k–kkk––––––fn, kn mmk[n]n mmPIC12(L)F1501 ENHANCED INSTRUCTION SET (CONTINUED)DescriptionRelative BranchRelative Branch with WCall SubroutineCall Subroutine with WGo to addressReturn from interruptReturn with literal in WReturn from SubroutineClear Watchdog TimerNo OperationLoad OPTION_REG register with WSoftware device ResetGo into Standby modeLoad TRIS register with WCyclesCONTROL OPERATIONS22222222INHERENT OPERATIONS111111C-COMPILER OPTIMIZEDAdd Literal k to FSRnMove Indirect FSRn to W with pre/post inc/decmodifier, mmMove INDFn to W, Indexed Indirect.Move W to Indirect FSRn with pre/post inc/decmodifier, mmMove W to INDFn, Indexed Indirect.1111MSb11001000100011000000000000001100110014-Bit Opcode001k00000kkk00001kkk0000010000000000000000000000000000000001000011110000kkkk0000kkkk0000kkkk0000kkkk00000110000001100000011001100nkk00010nkk0001LSbkkkk1011kkkk1010kkkk1001kkkk1000010000000010000100110fffkkkk0nmmkkkk1nmmkkkkStatusAffectedTO, PDTO, PDk[n]1 11 1111 1nkk2Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycleis executed as a NOP.2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will requireone additional instruction cycle.3: See Table in the MOVIW and MOVWI instruction descriptions.ZZNotes2, 322, 3DS41615A-page 214 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150126.2 Instruction DescriptionsADDFSRAdd Literal to FSRnANDLWAND literal with WSyntax:[ label ] ADDFSR FSRn, kOperands: -32 k 31n [ 0, 1]Operation: FSR(n) + k FSR(n)Status Affected: NoneDescription: The signed 6-bit literal ‘k’ is added tothe contents of the FSRnH:FSRnLregister pair.Syntax: [ label ] ANDLW kOperands: 0 k 255Operation: (W) .AND. (k) (W)Status Affected: ZDescription: The contents of W register areAND’ed with the eight-bit literal ‘k’.The result is placed in the W register.FSRn is limited to the range0000h-FFFFh. Moving beyond thesebounds will cause the FSR towrap-around.ADDLWAdd literal and WSyntax: [ label ] ADDLW kOperands: 0 k 255Operation: (W) + k (W)Status Affected: C, DC, ZDescription: The contents of the W register areadded to the eight-bit literal ‘k’ and theresult is placed in the W register.ANDWFAND W with fSyntax: [ label ] ANDWF f,dOperands: 0 f 127d 0,1Operation: (W) .AND. (f) (destination)Status Affected: ZDescription: AND the W register with register ‘f’. If‘d’ is ‘0’, the result is stored in the Wregister. If ‘d’ is ‘1’, the result is storedback in register ‘f’.ADDWFAdd W and fSyntax: [ label ] ADDWF f,dOperands: 0 f 127d 0,1Operation: (W) + (f) (destination)Status Affected: C, DC, ZDescription: Add the contents of the W registerwith register ‘f’. If ‘d’ is ‘0’, the result isstored in the W register. If ‘d’ is ‘1’, theresult is stored back in register ‘f’.ASRFArithmetic Right ShiftSyntax: [ label ] ASRF f {,d}Operands: 0 f 127d [0,1]Operation: (f) dest(f) dest,(f) C,Status Affected: C, ZDescription: The contents of register ‘f’ are shiftedone bit to the right through the Carryflag. The MSb remains unchanged. If‘d’ is ‘0’, the result is placed in W. If ‘d’is ‘1’, the result is stored back in register‘f’.ADDWFCADD W and CARRY bit to fregister f CSyntax: [ label ] ADDWFC f {,d}Operands: 0 f 127d [0,1]Operation: (W) + (f) + (C) destStatus Affected: C, DC, ZDescription: Add W, the Carry flag and data memorylocation ‘f’. If ‘d’ is ‘0’, the result isplaced in W. If ‘d’ is ‘1’, the result isplaced in data memory location ‘f’. 2011 Microchip Technology Inc. Preliminary DS41615A-page 215

PIC12(L)F1501BCFBit Clear fSyntax: [ label ] BCF f,bOperands: 0 f 1270 b 7Operation: 0 (f)Status Affected: NoneDescription: Bit ‘b’ in register ‘f’ is cleared.BTFSCBit Test f, Skip if ClearSyntax:[ label ] BTFSC f,bOperands: 0 f 1270 b 7Operation: skip if (f) = 0Status Affected: NoneDescription: If bit ‘b’ in register ‘f’ is ‘1’, the nextinstruction is executed.If bit ‘b’, in register ‘f’, is ‘0’, the nextinstruction is discarded, and a NOP isexecuted instead, making this a2-cycle instruction.BRARelative BranchSyntax:[ label ] BRA label[ label ] BRA $+kOperands: -256 label - PC + 1 255-256 k 255Operation: (PC) + 1 + k PCStatus Affected: NoneDescription: Add the signed 9-bit literal ‘k’ to thePC. Since the PC will have incrementedto fetch the next instruction,the new address will be PC + 1 + k.This instruction is a two-cycle instruction.This branch has a limited range.BTFSSBit Test f, Skip if SetSyntax:[ label ] BTFSS f,bOperands: 0 f 1270 b < 7Operation: skip if (f) = 1Status Affected: NoneDescription: If bit ‘b’ in register ‘f’ is ‘0’, the nextinstruction is executed.If bit ‘b’ is ‘1’, then the nextinstruction is discarded and a NOP isexecuted instead, making this a2-cycle instruction.BRWSyntax:Operands:Operation:Status Affected:Description:Relative Branch with W[ label ] BRWNone(PC) + (W) PCNoneAdd the contents of W (unsigned) tothe PC. Since the PC will have incrementedto fetch the next instruction,the new address will be PC + 1 + (W).This instruction is a two-cycle instruction.BSFBit Set fSyntax: [ label ] BSF f,bOperands: 0 f 1270 b 7Operation: 1 (f)Status Affected: NoneDescription: Bit ‘b’ in register ‘f’ is set.DS41615A-page 216 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501CALLCall SubroutineSyntax:[ label ] CALL kOperands: 0 k 2047Operation: (PC)+ 1 TOS,k PC,(PCLATH) PCStatus Affected: NoneDescription: Call Subroutine. First, return address(PC + 1) is pushed onto the stack.The eleven-bit immediate address isloaded into PC bits . The upperbits of the PC are loaded fromPCLATH. CALL is a two-cycle instruction.CLRWDTSyntax:Operands:Operation:Status Affected:Description:Clear Watchdog Timer[ label ] CLRWDTNone00h WDT0 WDT prescaler,1 TO1 PDTO, PDCLRWDT instruction resets the WatchdogTimer. It also resets the prescalerof the WDT.Status bits TO and PD are set.CALLWSyntax:Operands:Operation:Status Affected:Description:Subroutine Call With W[ label ] CALLWNone(PC) +1 TOS,(W) PC,(PCLATH) PCNoneSubroutine call with W. First, thereturn address (PC + 1) is pushedonto the return stack. Then, the contentsof W is loaded into PC,and the contents of PCLATH intoPC. CALLW is a two-cycleinstruction.COMFComplement fSyntax: [ label ] COMF f,dOperands: 0 f 127d [0,1]Operation: (f) (destination)Status Affected: ZDescription: The contents of register ‘f’ are complemented.If ‘d’ is ‘0’, the result isstored in W. If ‘d’ is ‘1’, the result isstored back in register ‘f’.CLRFClear fSyntax: [ label ] CLRF fOperands: 0 f 127Operation:00h (f)1 ZStatus Affected: ZDescription: The contents of register ‘f’ are clearedand the Z bit is set.CLRWClear WDECFDecrement fSyntax:[ label ] DECF f,dOperands: 0 f 127d [0,1]Operation: (f) - 1 (destination)Status Affected: ZDescription: Decrement register ‘f’. If ‘d’ is ‘0’, theresult is stored in the Wregister. If ‘d’ is ‘1’, the result is storedback in register ‘f’.Syntax:Operands:Operation:Status Affected:Description:[ label ] CLRWNone00h (W)1 ZZW register is cleared. Zero bit (Z) isset. 2011 Microchip Technology Inc. Preliminary DS41615A-page 217

PIC12(L)F1501DECFSZ Decrement f, Skip if 0Syntax:[ label ] DECFSZ f,dOperands: 0 f 127d [0,1]Operation: (f) - 1 (destination);skip if result = 0Status Affected: NoneDescription: The contents of register ‘f’ are decremented.If ‘d’ is ‘0’, the result is placedin the W register. If ‘d’ is ‘1’, the resultis placed back in register ‘f’.If the result is ‘1’, the next instruction isexecuted. If the result is ‘0’, then aNOP is executed instead, making it a2-cycle instruction.INCFSZ Increment f, Skip if 0Syntax: [ label ] INCFSZ f,dOperands: 0 f 127d [0,1]Operation: (f) + 1 (destination),skip if result = 0Status Affected: NoneDescription: The contents of register ‘f’ are incremented.If ‘d’ is ‘0’, the result is placedin the W register. If ‘d’ is ‘1’, the resultis placed back in register ‘f’.If the result is ‘1’, the next instruction isexecuted. If the result is ‘0’, a NOP isexecuted instead, making it a 2-cycleinstruction.GOTOUnconditional BranchIORLWInclusive OR literal with WSyntax: [ label ] GOTO kOperands: 0 k 2047Operation: k PCPCLATH PCStatus Affected: NoneDescription: GOTO is an unconditional branch. Theeleven-bit immediate value is loadedinto PC bits . The upper bits ofPC are loaded from PCLATH.GOTO is a two-cycle instruction.Syntax: [ label ] IORLW kOperands: 0 k 255Operation:(W) .OR. k (W)Status Affected: ZDescription: The contents of the W register areOR’ed with the eight-bit literal ‘k’. Theresult is placed in the W register.INCFIncrement fSyntax: [ label ] INCF f,dOperands: 0 f 127d [0,1]Operation: (f) + 1 (destination)Status Affected: ZDescription: The contents of register ‘f’ are incremented.If ‘d’ is ‘0’, the result is placedin the W register. If ‘d’ is ‘1’, the resultis placed back in register ‘f’.IORWFInclusive OR W with fSyntax: [ label ] IORWF f,dOperands: 0 f 127d [0,1]Operation: (W) .OR. (f) (destination)Status Affected: ZDescription: Inclusive OR the W register with register‘f’. If ‘d’ is ‘0’, the result is placed inthe W register. If ‘d’ is ‘1’, the result isplaced back in register ‘f’.DS41615A-page 218 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501LSLFLogical Left ShiftSyntax: [ label ] LSLF f {,d}Operands: 0 f 127d [0,1]Operation:(f) C(f) dest0 destStatus Affected: C, ZDescription: The contents of register ‘f’ are shiftedone bit to the left through the Carry flag.A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,the result is placed in W. If ‘d’ is ‘1’, theresult is stored back in register ‘f’.LSRFCLogical Right Shiftregister f 0Syntax: [ label ] LSRF f {,d}Operands: 0 f 127d [0,1]Operation:0 dest(f) dest,(f) C,Status Affected: C, ZDescription: The contents of register ‘f’ are shiftedone bit to the right through the Carryflag. A ‘0’ is shifted into the MSb. If ‘d’ is‘0’, the result is placed in W. If ‘d’ is ‘1’,the result is stored back in register ‘f’.MOVFMove fSyntax: [ label ] MOVF f,dOperands: 0 f 127d [0,1]Operation:(f) (dest)Status Affected: ZDescription: The contents of register f is moved toa destination dependent upon thestatus of d. If d = 0,destination is Wregister. If d = 1, the destination is fileregister f itself. d = 1 is useful to test afile register since status flag Z isaffected.Words: 1Cycles: 1Example: MOVF FSR, 0After InstructionW = value in FSR registerZ = 10register f C 2011 Microchip Technology Inc. Preliminary DS41615A-page 219

PIC12(L)F1501MOVIWMove INDFn to WMOVLPMove literal to PCLATHSyntax:[ label ] MOVIW ++FSRn[ label ] MOVIW --FSRn[ label ] MOVIW FSRn++[ label ] MOVIW FSRn--[ label ] MOVIW k[FSRn]Operands: n [0,1]mm [00,01, 10, 11]-32 k 31Operation:INDFn WEffective address is determined by• FSR + 1 (preincrement)• FSR - 1 (predecrement)• FSR + k (relative offset)After the Move, the FSR value will beeither:• FSR + 1 (all increments)• FSR - 1 (all decrements)• UnchangedStatus Affected: ZMode Syntax mmPreincrement ++FSRn 00Predecrement --FSRn 01Postincrement FSRn++ 10Postdecrement FSRn-- 11Description:This instruction is used to move databetween W and one of the indirectregisters (INDFn). Before/after thismove, the pointer (FSRn) is updated bypre/post incrementing/decrementing it.Note: The INDFn registers are notphysical registers. Any instruction thataccesses an INDFn register actuallyaccesses the register at the addressspecified by the FSRn.FSRn is limited to the range0000h-FFFFh.Incrementing/decrementing it beyondthese bounds will cause it towrap-around.Syntax:[ label ] MOVLP kOperands: 0 k 127Operation:k PCLATHStatus Affected: NoneDescription: The seven-bit literal ‘k’ is loaded into thePCLATH register.MOVLW Move literal to WSyntax: [ label ] MOVLW kOperands: 0 k 255Operation: k (W)Status Affected: NoneDescription: The eight-bit literal ‘k’ is loaded into Wregister. The “don’t cares” will assembleas ‘0’s.Words: 1Cycles: 1Example: MOVLW 0x5AAfter InstructionW = 0x5AMOVWFMove W to fSyntax: [ label ] MOVWF fOperands: 0 f 127Operation:(W) (f)Status Affected: NoneDescription: Move data from W register to register‘f’.Words: 1Cycles: 1Example: MOVWF OPTION_REGBefore InstructionOPTION_REG = 0xFFW= 0x4FAfter InstructionOPTION_REG = 0x4FW= 0x4FMOVLBMove literal to BSRSyntax:[ label ] MOVLB kOperands: 0 k 15Operation: k BSRStatus Affected: NoneDescription: The five-bit literal ‘k’ is loaded into theBank Select Register (BSR).DS41615A-page 220 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501MOVWIMove W to INDFnSyntax:[ label ] MOVWI ++FSRn[ label ] MOVWI --FSRn[ label ] MOVWI FSRn++[ label ] MOVWI FSRn--[ label ] MOVWI k[FSRn]Operands: n [0,1]mm [00,01, 10, 11]-32 k 31Operation:W INDFnEffective address is determined by• FSR + 1 (preincrement)• FSR - 1 (predecrement)• FSR + k (relative offset)After the Move, the FSR value will beeither:• FSR + 1 (all increments)• FSR - 1 (all decrements)UnchangedStatus Affected: NoneMode Syntax mmPreincrement ++FSRn 00Predecrement --FSRn 01Postincrement FSRn++ 10Postdecrement FSRn-- 11NOPNo OperationSyntax: [ label ] NOPOperands:NoneOperation:No operationStatus Affected: NoneDescription: No operationWords: 1Cycles: 1Example:NOPOPTIONSyntax:Operands:Operation:Status Affected:Description:RESETLoad OPTION_REG Registerwith W[ label ] OPTIONNone(W) OPTION_REGNoneMove data from W register toOPTION_REG register.Software ResetDescription:This instruction is used to move databetween W and one of the indirectregisters (INDFn). Before/after thismove, the pointer (FSRn) is updated bypre/post incrementing/decrementing it.Note: The INDFn registers are notphysical registers. Any instruction thataccesses an INDFn register actuallyaccesses the register at the addressspecified by the FSRn.Syntax:Operands:Operation:Status Affected:Description:[ label ] RESETNoneExecute a device Reset. Resets thenRI flag of the PCON register.NoneThis instruction provides a way toexecute a hardware Reset by software.FSRn is limited to the range0000h-FFFFh.Incrementing/decrementing it beyondthese bounds will cause it towrap-around.The increment/decrement operation onFSRn WILL NOT affect any Status bits. 2011 Microchip Technology Inc. Preliminary DS41615A-page 221

PIC12(L)F1501RETFIEReturn from InterruptSyntax: [ label ] RETFIE kOperands:NoneOperation:TOS PC,1 GIEStatus Affected: NoneDescription: Return from Interrupt. Stack is POPedand Top-of-Stack (TOS) is loaded inthe PC. Interrupts are enabled bysetting Global Interrupt Enable bit,GIE (INTCON). This is a two-cycleinstruction.Words: 1Cycles: 2Example:RETFIEAfter InterruptPC = TOSGIE = 1RETURNReturn from SubroutineSyntax: [ label ] RETURNOperands: NoneOperation: TOS PCStatus Affected: NoneDescription: Return from subroutine. The stack isPOPed and the top of the stack (TOS)is loaded into the program counter.This is a two-cycle instruction.RETLWReturn with literal in WSyntax: [ label ] RETLW kOperands: 0 k 255Operation:k (W);TOS PCStatus Affected: NoneDescription: The W register is loaded with the eightbit literal ‘k’. The program counter isloaded from the top of the stack (thereturn address). This is a two-cycleinstruction.Words: 1Cycles: 2Example:CALL TABLE;W contains table;offset value• ;W now has table valueTABLE••ADDWF PC ;W = offsetRETLW k1 ;Begin tableRETLW k2 ;•••RETLW kn ; End of tableRLFRotate Left f through CarrySyntax: [ label ] RLF f,dOperands: 0 f 127d [0,1]Operation:See description belowStatus Affected: CDescription: The contents of register ‘f’ are rotatedone bit to the left through the Carryflag. If ‘d’ is ‘0’, the result is placed inthe W register. If ‘d’ is ‘1’, the result isstored back in register ‘f’.C Register fWords: 1Cycles: 1Example: RLF REG1,0Before InstructionREG1 = 1110 0110C = 0After InstructionREG1 = 1110 0110W = 1100 1100C = 1Before InstructionW = 0x07After InstructionW = value of k8DS41615A-page 222 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501RRFRotate Right f through CarrySyntax: [ label ] RRF f,dOperands: 0 f 127d [0,1]Operation: See description belowStatus Affected: CDescription: The contents of register ‘f’ are rotatedone bit to the right through the Carryflag. If ‘d’ is ‘0’, the result is placed inthe W register. If ‘d’ is ‘1’, the result isplaced back in register ‘f’.CRegister fSUBLWSubtract W from literalSyntax: [ label ] SUBLW kOperands: 0 k 255Operation: k - (W) W)Status Affected: C, DC, ZDescription: The W register is subtracted (2’s complementmethod) from the eight-bitliteral ‘k’. The result is placed in the Wregister.C = 0C = 1DC = 0DC = 1W kW kW kW kSLEEPEnter Sleep modeSyntax: [ label ] SLEEPOperands:NoneOperation:00h WDT,0 WDT prescaler,1 TO,0 PDStatus Affected: TO, PDDescription: The power-down Status bit, PD iscleared. Time-out Status bit, TO isset. Watchdog Timer and its prescalerare cleared.The processor is put into Sleep modewith the oscillator stopped.SUBWFSubtract W from fSyntax: [ label ] SUBWF f,dOperands: 0 f 127d [0,1]Operation: (f) - (W) destination)Status Affected: C, DC, ZDescription: Subtract (2’s complement method) Wregister from register ‘f’. If ‘d’ is ‘0’, theresult is stored in the W register. If ‘d’ is‘1’, the result is stored back in register‘f.C = 0C = 1DC = 0DC = 1W fW fW fW fSUBWFBSubtract W from f with BorrowSyntax: SUBWFB f {,d}Operands: 0 f 127d [0,1]Operation: (f) – (W) – (B) destStatus Affected: C, DC, ZDescription: Subtract W and the BORROW flag(CARRY) from register ‘f’ (2’s complementmethod). If ‘d’ is ‘0’, the result isstored in W. If ‘d’ is ‘1’, the result isstored back in register ‘f’. 2011 Microchip Technology Inc. Preliminary DS41615A-page 223

PIC12(L)F1501SWAPFSwap Nibbles in fSyntax: [ label ] SWAPF f,dOperands: 0 f 127d [0,1]Operation: (f) (destination),(f) (destination)Status Affected: NoneDescription: The upper and lower nibbles of register‘f’ are exchanged. If ‘d’ is ‘0’, theresult is placed in the W register. If ‘d’is ‘1’, the result is placed in register ‘f’.XORLWExclusive OR literal with WSyntax: [ label ] XORLW kOperands:0 k 255Operation:(W) .XOR. k W)Status Affected: ZDescription: The contents of the W register areXOR’ed with the eight-bitliteral ‘k’. The result is placed in theW register.TRISLoad TRIS Register with WSyntax:[ label ] TRIS fOperands: 5 f 7Operation: (W) TRIS register ‘f’Status Affected: NoneDescription: Move data from W register to TRISregister.When ‘f’ = 5, TRISA is loaded.When ‘f’ = 6, TRISB is loaded.When ‘f’ = 7, TRISC is loaded.XORWFExclusive OR W with fSyntax: [ label ] XORWF f,dOperands: 0 f 127d [0,1]Operation: (W) .XOR. (f) destination)Status Affected: ZDescription: Exclusive OR the contents of the Wregister with register ‘f’. If ‘d’ is ‘0’, theresult is stored in the W register. If ‘d’is ‘1’, the result is stored back in register‘f’.DS41615A-page 224 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150127.0 ELECTRICAL SPECIFICATIONSAbsolute Maximum Ratings (†)Ambient temperature under bias....................................................................................................... -40°C to +125°CStorage temperature ........................................................................................................................ -65°C to +150°CVoltage on VDD with respect to VSS, PIC12F1501 ............................................................................. -0.3V to +6.5VVoltage on VDD with respect to VSS, PIC12LF1501 ........................................................................... -0.3V to +4.0VVoltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0VVoltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)Total power dissipation (1) ............................................................................................................................... 800 mWMaximum current out of VSS pin, -40°C TA +85°C for industrial............................................................... 210 mAMaximum current out of VSS pin, -40°C TA +125°C for extended .............................................................. 95 mAMaximum current into VDD pin, -40°C TA +85°C for industrial.................................................................. 150 mAMaximum current into VDD pin, -40°C TA +125°C for extended ................................................................. 70 mAClamp current, IK (VPIN < 0 or VPIN > VDD)20 mAMaximum output current sunk by any I/O pin.................................................................................................... 25 mAMaximum output current sourced by any I/O pin .............................................................................................. 25 mANote 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOl x IOL).† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to thedevice. This is a stress rating only and functional operation of the device at those or any other conditions above thoseindicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions forextended periods may affect device reliability. 2011 Microchip Technology Inc. Preliminary DS41615A-page 225

PIC12(L)F1501FIGURE 27-1:PIC12F1501 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C5.5VDD (V)2.52.304 10 1620Frequency (MHz)Note 1: The shaded region indicates the permissible combinations of voltage and frequency.2: Refer to Table 27-1 for each Oscillator mode’s supported frequencies.FIGURE 27-2:PIC12LF1501 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°CVDD (V)3.62.51.804 10 1620Frequency (MHz)Note 1: The shaded region indicates the permissible combinations of voltage and frequency.2: Refer to Table 27-1 for each Oscillator mode’s supported frequencies.DS41615A-page 226 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150127.1 DC Characteristics: PIC12(L)F1501-I/E (Industrial, Extended)Standard Operating Conditions (unless otherwise stated)PIC12LF1501Operating temperature -40°C TA +85°C for industrial-40°C TA +125°C for extendedStandard Operating Conditions (unless otherwise stated)PIC12F1501Operating temperature -40°C TA +85°C for industrial-40°C TA +125°C for extendedParam. Sym. Characteristic Min. Typ† Max. Units ConditionsNo.D001 VDD Supply VoltagePIC12LF1501 1.82.5D001 PIC12F1501 2.32.5D002* VDR RAM Data Retention Voltage (1)————3.63.65.55.5VVVVFOSC 16 MHz:FOSC 20 MHzFOSC 16 MHz:FOSC 20 MHzPIC12LF1501 1.5 — — V Device in Sleep modeD002* PIC12F1501 1.65 — — V Device in Sleep modeD002A* VPOR* Power-on Reset Release VoltagePIC12LF1501 — 1.6 — VD002A* PIC12F1501 — 1.7 — VD002B* VPORR* Power-on Reset Rearm VoltagePIC12LF1501 — 0.8 — VD002B* PIC12F1501 — 1.7 — VD003 VADFVR Fixed Voltage Reference Voltage forADC, Initial AccuracyD003C* TCVFVR Temperature Coefficient, FixedVoltage ReferenceD003D*VFVR/VINLine Regulation, Fixed VoltageReferenceD004* SVDD VDD Rise Rate to ensure internalPower-on Reset signal——————111111——————— -130 — ppm/°C— 0.270 — %/V% 1.024V, VDD 2.5V, 85°C (NOTE 2)1.024V, VDD 2.5V, 125°C (NOTE 2)2.048V, VDD 2.5V, 85°C2.048V, VDD 2.5V, 125°C4.096V, VDD 4.75V, 85°C4.096V, VDD 4.75V, 125°C0.05 — — V/ms See Section 6.1 “Power-on Reset(POR)” for details.* These parameters are characterized but not tested.† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are nottested.Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.2: For proper operation, the minimum value of the ADC positive voltage reference must be 1.8V or greater. When selecting theFVR or the VREF+ pin as the source of the ADC positive voltage reference, be aware that the voltage must be 1.8V orgreater. 2011 Microchip Technology Inc. Preliminary DS41615A-page 227

PIC12(L)F1501FIGURE 27-3:POR AND POR REARM WITH SLOW RISING VDDVDDVPORVPORRVSSNPORPOR REARMVSSTVLOW (2)TPOR (3)Note 1: When NPOR is low, the device is held in Reset.2: TPOR 1 s typical.3: TVLOW 2.7 s typical.DS41615A-page 228 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150127.2 DC Characteristics: PIC12(L)F1501-I/E (Industrial, Extended)PIC12LF1501PIC12F1501ParamNo.DeviceCharacteristicsStandard Operating Conditions (unless otherwise stated)Operating temperature -40°C TA +85°C for industrial-40°C TA +125°C for extendedStandard Operating Conditions (unless otherwise stated)Operating temperature -40°C TA +85°C for industrial-40°C TA +125°C for extendedMin. Typ† Max. UnitsVDDConditions(1, 2)Supply Current (IDD)D013 — 25 140 A 1.8 FOSC = 1 MHz— 45 230 A 3.0 EC Oscillator mode, Medium-power modeD013 — 60 180 A 2.3 FOSC = 1 MHz— 80 240 A 3.0 EC Oscillator modeMedium-power mode— 100 320 A 5.0D014 — 100 250 A 1.8 FOSC = 4 MHz— 180 430 A 3.0 EC Oscillator mode,Medium-power modeD014 — 160 275 A 2.3 FOSC = 4 MHz— 210 450 A 3.0 EC Oscillator modeMedium-power mode— 260 650 A 5.0D015 — 2.5 18 A 1.8 FOSC = 31 kHz— 4.0 20 A 3.0 LFINTOSC modeD015 — 14 58 A 2.3 FOSC = 31 kHz— 15 65 A 3.0 LFINTOSC mode— 16 70 A 5.0D017* — 0.40 0.70 mA 1.8 FOSC = 8 MHz— 0.60 1.10 mA 3.0 HFINTOSC modeD017* — 0.50 0.75 mA 2.3 FOSC = 8 MHz— 0.60 1.15 mA 3.0 HFINTOSC mode— 0.70 1.35 mA 5.0D018 — 0.60 1.2 mA 1.8 FOSC = 16 MHz— 1.0 1.75 mA 3.0 HFINTOSC modeD018 — 0.74 1.2 mA 2.3 FOSC = 16 MHz— 0.96 1.8 mA 3.0 HFINTOSC mode— 1.03 2.0 mA 5.0D019A — 6 17 A 1.8 FOSC = 32 kHz— 8 20 A 3.0 ECL modeD019A — 14 25 A 3.0 FOSC = 32 kHz— 15 30 A 5.0 ECL modeD019B — 15 165 A 1.8 FOSC = 500 kHz— 20 190 A 3.0 ECM mode* These parameters are characterized but not tested.† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are nottested.Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, fromrail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loadingand switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the currentconsumption.Note 2011 Microchip Technology Inc. Preliminary DS41615A-page 229

PIC12(L)F150127.2 DC Characteristics: PIC12(L)F1501-I/E (Industrial, Extended) (Continued)PIC12LF1501PIC12F1501ParamNo.DeviceCharacteristics(1, 2)Supply Current (IDD)Standard Operating Conditions (unless otherwise stated)Operating temperature -40°C TA +85°C for industrial-40°C TA +125°C for extendedStandard Operating Conditions (unless otherwise stated)Operating temperature -40°C TA +85°C for industrial-40°C TA +125°C for extendedMin. Typ† Max. UnitsConditionsD019B — 34 210 A 3.0 FOSC = 500 kHz— 37 270 A 5.0 ECM modeD019C — 0.65 — mA 3.0 FOSC = 20 MHzECH modeD019C — 0.75 — mA 3.0 FOSC = 20 MHz— 0.87 — mA 5.0 ECH mode* These parameters are characterized but not tested.† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are nottested.Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, fromrail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loadingand switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the currentconsumption.VDDNoteDS41615A-page 230 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150127.3 DC Characteristics: PIC12(L)F1501-I/E (Power-Down)PIC12LF1501PIC12F1501ParamNo.Device Characteristics Min. Typ†Standard Operating Conditions (unless otherwise stated)Operating temperature -40°C TA +85°C for industrial-40°C TA +125°C for extendedStandard Operating Conditions (unless otherwise stated)Operating temperature -40°C TA +85°C for industrial-40°C TA +125°C for extendedMax.+85°CMax.Conditions+125°C Units VDDNotePower-down Base Current (IPD) (2)D022 — .02 1.0 2.4 A 1.8 WDT, BOR, FVR, and T1OSC— .03 1.1 3.0 A 3.0 disabled, all Peripherals InactiveD022 — 10 35 40 A 2.3 WDT, BOR, FVR, and T1OSC— 11 42 48 A 3.0 disabled, all Peripherals Inactive— 12 45 61 A 5.0D023 — 0.2 1.5 2.4 A 1.8 LPWDT Current (Note 1)— 0.5 2.0 3.0 A 3.0D023 — 11 38 44 A 2.3 LPWDT Current (Note 1)— 12 43 48 A 3.0— 13 48 65 A 5.0D023A — 13 22 25 A 1.8 FVR current (Note 1)— 22 24 27 A 3.0D023A — 23 62 65 A 2.3 FVR current (Note 1)— 30 72 75 A 3.0— 34 115 120 A 5.0D024 — 7 14 16 A 3.0 BOR Current (Note 1)D024 — 15 47 50 A 3.0 BOR Current (Note 1)— 17 55 66 A 5.0D024A — 0.2 5 7 A 3.0 LPBOR CurrentD024A — 10 25 40 A 3.0 LPBOR Current— 12 30 50 A 5.0D026 — 0.03 3.5 4.0 A 1.8 A/D Current (Note 1, Note 3), no— 0.04 4.0 4.5 A 3.0 conversion in progressD026 — 10 39 45 A 2.3 A/D Current (Note 1, Note 3), no— 11 43 49 A 3.0 conversion in progress— 12 46 65 A 5.0D026A* — 250 1.5 3.0 A 1.8 A/D Current (Note 1, Note 3),— 250 2.0 3.5 A 3.0 conversion in progressD026A* — 280 38 45 A 2.3 A/D Current (Note 1, Note 3),— 280 43 49 A 3.0 conversion in progress— 280 46 65 A 5.0* These parameters are characterized but not tested.† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and arenot tested.Legend: TBD = To Be DeterminedNote 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral isenabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Maxvalues should be used when calculating total current consumption.2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured withthe part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.3: A/D oscillator source is FRC. 2011 Microchip Technology Inc. Preliminary DS41615A-page 231

PIC12(L)F150127.3 DC Characteristics: PIC12(L)F1501-I/E (Power-Down) (Continued)PIC12LF1501PIC12F1501ParamNo.Device Characteristics Min. Typ†Power-down Base Current (IPD) (2)Standard Operating Conditions (unless otherwise stated)Operating temperature -40°C TA +85°C for industrial-40°C TA +125°C for extendedStandard Operating Conditions (unless otherwise stated)Operating temperature -40°C TA +85°C for industrial-40°C TA +125°C for extendedMax.+85°CMax.Conditions+125°C Units VDDNoteD027* — 20 43 55 A 1.8 1 Comparator Enabled— 21 45 60 A 3.0 (HP Mode)D027* — 30 53 65 A 2.3 1 Comparator Enabled— 31 57 70 A 3.0 (HP Mode)— 32 61 75 A 5.0D027A* — 7 20 35 A 1.8 1 Comparator Enabled— 80 25 40 A 3.0 (LP Mode)D027A* — 17 30 45 A 2.3 1 Comparator Enabled— 18 37 55 A 3.0 (LP Mode)— 19 40 60 A 5.0D028* — 21 44 56 A 1.8 2 Comparators Enabled— 22 46 61 A 3.0 (HP Mode)D028* — 31 54 66 A 2.3 2 Comparators Enabled— 32 58 71 A 3.0 (HP Mode)— 33 62 76 A 5.0D028A* — 8 21 36 A 1.8 2 Comparators Enabled— 81 26 41 A 3.0 (LP Mode)D028A* — 18 31 46 A 2.3 2 Comparators Enabled— 19 38 56 A 3.0 (LP Mode)— 20 41 61 A 5.0* These parameters are characterized but not tested.† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and arenot tested.Legend: TBD = To Be DeterminedNote 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral isenabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Maxvalues should be used when calculating total current consumption.2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured withthe part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.3: A/D oscillator source is FRC.DS41615A-page 232 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150127.3 DC Characteristics: PIC12(L)F1501-I/E (Power-Down) (Continued)PIC12LF1501PIC12F1501ParamNo.Device Characteristics Min. Typ†Standard Operating Conditions (unless otherwise stated)Operating temperature -40°C TA +85°C for industrial-40°C TA +125°C for extendedStandard Operating Conditions (unless otherwise stated)Operating temperature -40°C TA +85°C for industrial-40°C TA +125°C for extendedMax.+85°CMax.Conditions+125°C Units VDDNotePower-down Base Current (IPD) in Low-Power Sleep mode (2)D029A — 0.1 1.5 2.0 A 2.3 Base0.2 1.7 2.3 A 3.00.3 1.9 2.5 A 5.0D029B — 18 40 45 A 2.3 FVR Enabled18.5 45 50 A 3.019 47 52 A 5.0D029C — 8.0 20 25 A 3.0 BOR Enabled9.5 24 30 A 5.0D029D — 3.2 13 18 A 2.3 Comparator Enabled3.5 14 19 A 3.0 (LP mode)3.6 15 20 A 5.0D029E — 17.0 40 45 A 2.3 Comparator Enabled17.5 42 47 A 3.0 (HP mode)18.0 43 48 A 5.0* These parameters are characterized but not tested.† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and arenot tested.Legend: TBD = To Be DeterminedNote 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral isenabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Maxvalues should be used when calculating total current consumption.2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured withthe part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.3: A/D oscillator source is FRC. 2011 Microchip Technology Inc. Preliminary DS41615A-page 233

PIC12(L)F150127.4 DC Characteristics: PIC12(L)F1501-I/EParamNo.DC CHARACTERISTICSStandard Operating Conditions (unless otherwise stated)Operating temperature -40°C TA +85°C for industrial-40°C TA +125°C for extendedSym. Characteristic Min. Typ† Max. Units ConditionsVILInput Low VoltageI/O PORT:D030 with TTL buffer — — 0.8 V 4.5V VDD 5.5VD030A — — 0.15 VDD V 1.8V VDD 4.5VD031 with Schmitt Trigger buffer — — 0.2 VDD V 2.0V VDD 5.5VD032 MCLR — — 0.2 VDD VVIH Input High VoltageI/O ports: — —D040 with TTL buffer 2.0 — — V 4.5V VDD 5.5VD040A 0.25 VDD + — — V 1.8V VDD 4.5V0.8D041 with Schmitt Trigger buffer 0.8 VDD — — V 2.0V VDD 5.5VD042 MCLR 0.8 VDD — — VIIL Input Leakage Current (1)D060 I/O ports — ± 5± 5± 125± 1000nAnAVSS VPIN VDD, Pin at highimpedanceat 85°C125°CD061 MCLR (2) — ± 50 ± 200 nA VSS VPIN VDD at 85°CIPUR Weak Pull-up CurrentD070* 2525VOL Output Low Voltage (3)D080D090I/O portsVOH Output High Voltage (3)I/O ports100140200300 A— — 0.6 VVDD - 0.7 — — VVDD = 3.3V, VPIN = VSSVDD = 5.0V, VPIN = VSSIOL = 8mA, VDD = 5VIOL = 6mA, VDD = 3.3VIOL = 1.8mA, VDD = 1.8VIOH = 3.5mA, VDD = 5VIOH = 3mA, VDD = 3.3VIOH = 1mA, VDD = 1.8VCapacitive Loading Specs on Output PinsD101A* CIO All I/O pins — — 50 pF* These parameters are characterized but not tested.† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and arenot tested.Note 1: Negative current is defined as current sourced by the pin.2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels representnormal operating conditions. Higher leakage current may be measured at different input voltages.3: Including OSC2 in CLKOUT mode.DS41615A-page 234 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150127.5 Memory Programming RequirementsDC CHARACTERISTICSParamNo.Standard Operating Conditions (unless otherwise stated)Operating temperature -40°C TA +125°CSym. Characteristic Min. Typ† Max. Units ConditionsProgram Memory ProgrammingSpecificationsD110 VIHH Voltage on MCLR/VPP pin 8.0 — 9.0 V (Note 2)D111 IDDP Supply Current during Programming — — 10 mAD112 VBE VDD for Bulk Erase 2.7 — VDD max. VD113 VPEW VDD for Write or Row Erase VDD min. — VDD max. VD114 IPPPGM Current on MCLR/VPP during Erase/ — 1.0 — mAWriteD115 IDDPGM Current on VDD during Erase/Write — 5.0 — mAProgram Flash MemoryD121 EP Cell Endurance 10K — — E/W -40C to +85C (Note 1)D122 VPR VDD for Read VDD min. — VDD max. VD123 TIW Self-timed Write Cycle Time — 2 2.5 msD124 TRETD Characteristic Retention — 40 — Year Provided no otherspecifications are violatedD125 EHEFC High-Endurance Flash Cell 100K — — E/W 0C to +60C,Lower byte,Last 128 Addresses in FlashMemory† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and arenot tested.Note 1: Self-write and Block Erase.2: Required only if single-supply programming is disabled. 2011 Microchip Technology Inc. Preliminary DS41615A-page 235

PIC12(L)F150127.6 Thermal ConsiderationsStandard Operating Conditions (unless otherwise stated)Operating temperature -40°C TA +125°CParamNo.Sym. Characteristic Typ. Units ConditionsTH01 JA Thermal Resistance Junction to Ambient 89.3 C/W 8-pin PDIP package149.5 C/W 8-pin SOIC package211 C/W 8-pin MSOP package56.7 C/W 8-pin DFN 3X3mm package68 C/W 8-pin DFN 2X3mm packageTH02 JC Thermal Resistance Junction to Case 43.1 C/W 8-pin PDIP package39.9 C/W 8-pin SOIC package39 C/W 8-pin MSOP package9 C/W 8-pin DFN 3X3mm package12.7 C/W 8-pin DFN 2X3mm packageTH03 TJMAX Maximum Junction Temperature 150 CTH04 PD Power Dissipation — W PD = PINTERNAL + PI/OTH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD (1)TH06 PI/O I/O Power Dissipation — W PI/O = (IOL * VOL) + (IOH * (VDD - VOH))TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA (2)Note 1: IDD is current to run the chip alone without driving any load on the output pins.2: TA = Ambient Temperature.3: TJ = Junction Temperature.DS41615A-page 236 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150127.7 Timing Parameter SymbologyThe timing parameter symbols have been created withone of the following formats:1. TppS2ppS2. TppSTF Frequency T TimeLowercase letters (pp) and their meanings:ppcc CCP1 osc CLKINck CLKOUT rd RDcs CS rw RD or WRdi SDIx sc SCKxdo SDO ss SSdt Data in t0 T0CKIio I/O PORT t1 T1CKImc MCLR wr WRUppercase letters and their meanings:SF Fall P PeriodH High R RiseI Invalid (High-impedance) V ValidL Low Z High-impedanceFIGURE 27-4:LOAD CONDITIONSLoad ConditionPinCLVSSLegend:CL = 50 pF for all pins 2011 Microchip Technology Inc. Preliminary DS41615A-page 237

PIC12(L)F150127.8 AC Characteristics: PIC12(L)F1501-I/EFIGURE 27-5:CLOCK TIMINGQ4 Q1 Q2 Q3 Q4 Q1CLKINOS02OS12OS11OS03CLKOUT(CLKOUT Mode)Note 1: See Table 27-3.TABLE 27-1:CLOCK OSCILLATOR TIMING REQUIREMENTSStandard Operating Conditions (unless otherwise stated)Operating temperature -40°C TA +125°CParamNo.Sym. Characteristic Min. Typ† Max. Units ConditionsOS01 FOSC External CLKIN Frequency (1) DC — 0.5 MHz EC Oscillator mode (low)DC — 4 MHz EC Oscillator mode (medium)DC — 20 MHz EC Oscillator mode (high)OS02 TOSC External CLKIN Period (1) 50 — ns EC modeOS03 TCY Instruction Cycle Time (1) 200 — DC ns TCY = FOSC/4* These parameters are characterized but not tested.† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are nottested.Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based oncharacterization data for that particular oscillator type under standard operating conditions with the device executing code.Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption.All devices are tested to operate at “min” values with an external clock applied to CLKIN pin. When an externalclock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.TABLE 27-2: OSCILLATOR PARAMETERSStandard Operating Conditions (unless otherwise stated)Operating Temperature -40°C TA +125°CParamNo.Sym.CharacteristicFreq.ToleranceMin. Typ† Max. Units Conditions10% — 16.0 — MHz 0°C TA +85°COS08 HFOSC Internal Calibrated HFINTOSCFrequency (1)OS09 LFOSC Internal LFINTOSC Frequency — — 31 — kHz -40°C TA +125°COS10* TIOSC ST HFINTOSC— — 5 8 sWake-up from Sleep Start-up Time* These parameters are characterized but not tested.† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and arenot tested.Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device aspossible. 0.1 F and 0.01 F values in parallel are recommended.DS41615A-page 238 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501FIGURE 27-6:CLKOUT AND I/O TIMINGCycleWrite Fetch Read ExecuteQ4 Q1 Q2 Q3FOSCOS11OS12CLKOUTOS20OS21OS19OS13OS17OS16OS18I/O pin(Input)OS15OS14I/O pin(Output)Old ValueNew ValueOS18, OS19TABLE 27-3:CLKOUT AND I/O TIMING PARAMETERSStandard Operating Conditions (unless otherwise stated)Operating Temperature -40°C TA +125°CParamNo.Sym. Characteristic Min. Typ† Max. Units ConditionsOS11 TosH2ckL FOSC to CLKOUT (1) — — 70 ns VDD = 3.3-5.0VOS12 TosH2ckH FOSC to CLKOUT (1) — — 72 ns VDD = 3.3-5.0VOS13 TckL2ioV CLKOUT to Port out valid (1) — — 20 nsOS14 TioV2ckH Port input valid before CLKOUT (1) TOSC + 200 ns — — nsOS15 TosH2ioV Fosc (Q1 cycle) to Port out valid — 50 70* ns VDD = 3.3-5.0VOS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid 50 — — ns VDD = 3.3-5.0V(I/O in hold time)OS17 TioV2osH Port input valid to Fosc(Q2 cycle)(I/O in setup time)20 — — nsOS18* TioR Port output rise time (2) ——OS19* TioF Port output fall time (2) ——OS20* Tinp INT pin input high or low time 25 — — nsOS21* Tioc Interrupt-on-change new input level25 — — nstime* These parameters are characterized but not tested.† Data in “Typ” column is at 3.0V, 25C unless otherwise stated.Note 1: Measurements are taken in EC mode where CLKOUT output is 4 x TOSC.1540281532725530ns VDD = 2.0VVDD = 5.0Vns VDD = 2.0VVDD = 5.0V 2011 Microchip Technology Inc. Preliminary DS41615A-page 239

PIC12(L)F1501FIGURE 27-7:RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UPTIMER TIMINGVDDMCLRInternalPOR30PWRTTime-out33Internal Reset (1)Watchdog TimerReset (1)343134I/O pinsNote 1:Asserted low.FIGURE 27-8:BROWN-OUT RESET TIMING AND CHARACTERISTICSVDDVBORVBOR and VHYST(Device in Brown-out Reset)(Device not in Brown-out Reset)37Reset(due to BOR)33 (1)Note 1: 64 ms delay only if PWRTE bit in the Configuration Words is programmed to ‘0’.2 ms delay if PWRTE = 0 and VREGEN = 1.DS41615A-page 240 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501TABLE 27-4:RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMERAND BROWN-OUT RESET PARAMETERSStandard Operating Conditions (unless otherwise stated)Operating Temperature -40°C TA +125°CParamNo.Sym. Characteristic Min. Typ† Max. Units Conditions30 TMCL MCLR Pulse Width (low) 2531 TWDTLP Low-Power Watchdog TimerTime-out Period————ssVDD = 3.3-5V, -40°C to +85°CVDD = 3.3-5V10 16 27 ms VDD = 3.3V-5V,1:16 Prescaler used33* TPWRT Power-up Timer Period, PWRTE = 0 40 65 140 ms34* TIOZ I/O high-impedance from MCLR Low — — 2.0 sor Watchdog Timer Reset35 VBOR Brown-out Reset Voltage: BORV = 0 2.55 2.70 2.85 VBORV = 12.301.802.401.902.552.05VVPIC12(L)F1501PIC12F1501PIC12LF150136* VHYST Brown-out Reset Hysteresis 0 25 50 mV -40°C to +85°C37* TBORDC Brown-out Reset DC Response 1 3 5 s VDD VBORTime* These parameters are characterized but not tested.† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidanceonly and are not tested.Note 1: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device aspossible. 0.1 F and 0.01 F values in parallel are recommended.FIGURE 27-9:TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGST0CKI40 4142T1CKI45 4647 49TMR0 orTMR1 2011 Microchip Technology Inc. Preliminary DS41615A-page 241

PIC12(L)F1501TABLE 27-5:TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTSStandard Operating Conditions (unless otherwise stated)Operating Temperature -40°C TA +125°CParamNo.Sym. Characteristic Min. Typ† Max. Units Conditions40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — nsWith Prescaler 10 — — ns41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — nsWith Prescaler 10 — — ns42* TT0P T0CKI Period Greater of:20 or TCY + 40N45* TT1H T1CKI HighTime46* TT1L T1CKI LowTime47* TT1P T1CKI InputPeriodSynchronous, No Prescaler 0.5 TCY + 20 — — nsSynchronous,15 — — nswith PrescalerAsynchronous 30 — — nsSynchronous, No Prescaler 0.5 TCY + 20 — — nsSynchronous, with Prescaler 15 — — nsAsynchronous 30 — — nsSynchronous49* TCKEZTMR1 Delay from External Clock Edge to TimerIncrementGreater of:30 or TCY + 40NAsynchronous 60 — — nsTABLE 27-6: PIC12(L)F1501 A/D CONVERTER (ADC) CHARACTERISTICS:Standard Operating Conditions (unless otherwise stated)Operating temperature Tested at 25°C— — ns N = prescale value(2, 4, ..., 256)— — ns N = prescale value(1, 2, 4, 8)2 TOSC — 7 TOSC — Timers in Syncmode* These parameters are characterized but not tested.† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are nottested.Note 1: For proper operation, the minimum value of the ADC positive voltage reference must be 1.8V or greater. When selectingthe FVR or the VREF+ pin as the source of the ADC positive voltage reference, be aware that the voltage must be 1.8Vor greater.ParamNo.Sym. Characteristic Min. Typ† Max. Units ConditionsAD01 NR Resolution — — 10 bitAD02 EIL Integral Error — — ±1.7 LSb VREF = 3.0VAD03 EDL Differential Error — — ±1 LSb No missing codesVREF = 3.0VAD04 EOFF Offset Error — — ±2.5 LSb VREF = 3.0VAD05 EGN Gain Error — — ±2.0 LSb VREF = 3.0VAD06 VREF Reference Voltage (3) 1.8 — VDD V VREF = (VREF+ minus VREF-) (NOTE 5)AD07 VAIN Full-Scale Range VSS — VREF VAD08 ZAIN Recommended Impedance ofAnalog Voltage Source— — 10 k Can go higher if external 0.01F capacitor ispresent on input pin.* These parameters are characterized but not tested.† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are nottested.Note 1: Total Absolute Error includes integral, differential, offset and gain errors.2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.3: ADC VREF is from external VREF+ pin, VDD pin, whichever is selected as reference input.4: When ADC is off, it will not consume any current other than leakage current. The power-down current specificationincludes any such leakage from the ADC module.5: FVR voltage selected must be 2.048V or 4.096V.DS41615A-page 242 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501TABLE 27-7:PIC12(L)F1501 A/D CONVERSION REQUIREMENTSStandard Operating Conditions (unless otherwise stated)Operating temperature -40°C TA +125°CParamNo.Sym. Characteristic Min. Typ† Max. Units ConditionsAD130* TAD A/D Clock Period 1.0 — 9.0 s TOSC-basedA/D Internal FRC Oscillator 1.0 1.6 6.0 s ADCS = 11 (ADFRC mode)PeriodAD131 TCNV Conversion Time (not includingAcquisition Time) (1) — 11 — TAD Set GO/DONE bit to conversioncompleteAD132* TACQ Acquisition Time — 5.0 — s* These parameters are characterized but not tested.† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are nottested.Note 1: The ADRES register may be read on the following TCY cycle.FIGURE 27-10:PIC12(L)F1501 A/D CONVERSION TIMING (NORMAL MODE)BSF ADCON0, GOAD134 (TOSC/2 (1) )Q4AD131AD1301 TCYA/D CLKA/D Data9 8 7 6 3 2 1 0ADRESOLD_DATANEW_DATAADIF1 TCYGODONESampleAD132Sampling StoppedNote 1:If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows theSLEEP instruction to be executed. 2011 Microchip Technology Inc. Preliminary DS41615A-page 243

PIC12(L)F1501FIGURE 27-11:PIC12(L)F1501 A/D CONVERSION TIMING (SLEEP MODE)BSF ADCON0, GOAD134Q4(TOSC/2 + TCY (1) )AD131AD1301 TCYA/D CLKA/D Data9 8 7 6 3 2 1 0ADRESOLD_DATANEW_DATAADIF1 TCYGODONESampleAD132Sampling StoppedNote 1:If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows theSLEEP instruction to be executed.DS41615A-page 244 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501TABLE 27-8:COMPARATOR SPECIFICATIONSOperating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated).ParamNo.Sym. Characteristics Min. Typ. Max. Units CommentsCM01 Vioff Input Offset Voltage — ±7.5 ±60 mV High Power Mode,Vicm = VDD/2CM02 Vicm Input Common Mode Voltage 0 — VDD VCM03* CMRR Common Mode Rejection Ratio — 50 — dBCM04AResponse Time Rising Edge — 400 800 ns High Power ModeCM04B Response Time Falling Edge — 200 400 ns High Power ModeTrespCM04C Response Time Rising Edge — 1200 — ns Low Power ModeCM04D Response Time Falling Edge — 550 — nsCM05* Tmc2ov Comparator Mode Change to — — 10 sOutput ValidCM06 Chyster Comparator Hysteresis — 65 — mV Hysteresis ON* These parameters are characterized but not tested.TABLE 27-9: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONSOperating Conditions: 2.5V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated).ParamNo.Sym. Characteristics Min. Typ. Max. Units CommentsDAC01* CLSB Step Size — VDD/32 — VDAC02* CACC Absolute Accuracy — — 1/2 LSbDAC03* CR Unit Resistor Value (R) — 5000 — DAC04* CST Settling Time (1) — — 10 s* These parameters are characterized but not tested.Note 1: Settling time measured while DACR transitions from ‘0000’ to ‘1111’. 2011 Microchip Technology Inc. Preliminary DS41615A-page 245

PIC12(L)F1501NOTES:DS41615A-page 246 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150128.0 DC AND ACCHARACTERISTICS GRAPHSAND CHARTSGraphs and charts are not available at this time. 2011 Microchip Technology Inc. Preliminary DS41615A-page 247

PIC12(L)F1501NOTES:DS41615A-page 248 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150129.0 DEVELOPMENT SUPPORTThe PIC ® microcontrollers and dsPIC ® digital signalcontrollers are supported with a full range of softwareand hardware development tools:• Integrated Development Environment- MPLAB ® IDE Software• Compilers/Assemblers/Linkers- MPLAB C Compiler for Various DeviceFamilies- HI-TECH C ® for Various Device Families- MPASM TM Assembler- MPLINK TM Object Linker/MPLIB TM Object Librarian- MPLAB Assembler/Linker/Librarian forVarious Device Families• Simulators- MPLAB SIM Software Simulator• Emulators- MPLAB REAL ICE In-Circuit Emulator• In-Circuit Debuggers- MPLAB ICD 3- PICkit 3 Debug Express• Device Programmers- PICkit 2 Programmer- MPLAB PM3 Device Programmer• Low-Cost Demonstration/Development Boards,Evaluation Kits, and Starter Kits29.1 MPLAB Integrated DevelopmentEnvironment SoftwareThe MPLAB IDE software brings an ease of softwaredevelopment previously unseen in the 8/16/32-bitmicrocontroller market. The MPLAB IDE is a Windows ®operating system-based application that contains:• A single graphical interface to all debugging tools- Simulator- Programmer (sold separately)- In-Circuit Emulator (sold separately)- In-Circuit Debugger (sold separately)• A full-featured editor with color-coded context• A multiple project manager• Customizable data windows with direct edit ofcontents• High-level source code debugging• Mouse over variable inspection• Drag and drop variables from source to watchwindows• Extensive on-line help• Integration of select third party tools, such asIAR C CompilersThe MPLAB IDE allows you to:• Edit your source files (either C or assembly)• One-touch compile or assemble, and download toemulator and simulator tools (automaticallyupdates all project information)• Debug using:- Source files (C or assembly)- Mixed C and assembly- Machine codeMPLAB IDE supports multiple debugging tools in asingle development paradigm, from the cost-effectivesimulators, through low-cost in-circuit debuggers, tofull-featured emulators. This eliminates the learningcurve when upgrading to tools with increased flexibilityand power. 2011 Microchip Technology Inc. Preliminary DS41615A-page 249

PIC12(L)F150129.2 MPLAB C Compilers for VariousDevice FamiliesThe MPLAB C Compiler code development systemsare complete ANSI C compilers for Microchip’s PIC18,PIC24 and PIC32 families of microcontrollers and thedsPIC30 and dsPIC33 families of digital signal controllers.These compilers provide powerful integrationcapabilities, superior code optimization and ease ofuse.For easy source level debugging, the compilers providesymbol information that is optimized to the MPLAB IDEdebugger.29.3 HI-TECH C for Various DeviceFamiliesThe HI-TECH C Compiler code development systemsare complete ANSI C compilers for Microchip’s PICfamily of microcontrollers and the dsPIC family of digitalsignal controllers. These compilers provide powerfulintegration capabilities, omniscient code generationand ease of use.For easy source level debugging, the compilers providesymbol information that is optimized to the MPLAB IDEdebugger.The compilers include a macro assembler, linker, preprocessor,and one-step driver, and can run on multipleplatforms.29.4 MPASM AssemblerThe MPASM Assembler is a full-featured, universalmacro assembler for PIC10/12/16/18 MCUs.The MPASM Assembler generates relocatable objectfiles for the MPLINK Object Linker, Intel ® standard HEXfiles, MAP files to detail memory usage and symbolreference, absolute LST files that contain source linesand generated machine code and COFF files fordebugging.The MPASM Assembler features include:• Integration into MPLAB IDE projects• User-defined macros to streamlineassembly code• Conditional assembly for multi-purposesource files• Directives that allow complete control over theassembly process29.5 MPLINK Object Linker/MPLIB Object LibrarianThe MPLINK Object Linker combines relocatableobjects created by the MPASM Assembler and theMPLAB C18 C Compiler. It can link relocatable objectsfrom precompiled libraries, using directives from alinker script.The MPLIB Object Librarian manages the creation andmodification of library files of precompiled code. Whena routine from a library is called from a source file, onlythe modules that contain that routine will be linked inwith the application. This allows large libraries to beused efficiently in many different applications.The object linker/library features include:• Efficient linking of single libraries instead of manysmaller files• Enhanced code maintainability by groupingrelated modules together• Flexible creation of libraries with easy modulelisting, replacement, deletion and extraction29.6 MPLAB Assembler, Linker andLibrarian for Various DeviceFamiliesMPLAB Assembler produces relocatable machinecode from symbolic assembly language for PIC24,PIC32 and dsPIC devices. MPLAB C Compiler usesthe assembler to produce its object file. The assemblergenerates relocatable object files that can then bearchived or linked with other relocatable object files andarchives to create an executable file. Notable featuresof the assembler include:• Support for the entire device instruction set• Support for fixed-point and floating-point data• Command line interface• Rich directive set• Flexible macro language• MPLAB IDE compatibilityDS41615A-page 250 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150129.7 MPLAB SIM Software SimulatorThe MPLAB SIM Software Simulator allows codedevelopment in a PC-hosted environment by simulatingthe PIC MCUs and dsPIC ® DSCs on an instructionlevel. On any given instruction, the data areas can beexamined or modified and stimuli can be applied froma comprehensive stimulus controller. Registers can belogged to files for further run-time analysis. The tracebuffer and logic analyzer display extend the power ofthe simulator to record and track program execution,actions on I/O, most peripherals and internal registers.The MPLAB SIM Software Simulator fully supportssymbolic debugging using the MPLAB C Compilers,and the MPASM and MPLAB Assemblers. The softwaresimulator offers the flexibility to develop anddebug code outside of the hardware laboratory environment,making it an excellent, economical softwaredevelopment tool.29.8 MPLAB REAL ICE In-CircuitEmulator SystemMPLAB REAL ICE In-Circuit Emulator System isMicrochip’s next generation high-speed emulator forMicrochip Flash DSC and MCU devices. It debugs andprograms PIC ® Flash MCUs and dsPIC ® Flash DSCswith the easy-to-use, powerful graphical user interface ofthe MPLAB Integrated Development Environment (IDE),included with each kit.The emulator is connected to the design engineer’s PCusing a high-speed USB 2.0 interface and is connectedto the target with either a connector compatible with incircuitdebugger systems (RJ11) or with the new highspeed,noise tolerant, Low-Voltage Differential Signal(LVDS) interconnection (CAT5).The emulator is field upgradable through future firmwaredownloads in MPLAB IDE. In upcoming releases ofMPLAB IDE, new devices will be supported, and newfeatures will be added. MPLAB REAL ICE offerssignificant advantages over competitive emulatorsincluding low-cost, full-speed emulation, run-timevariable watches, trace analysis, complex breakpoints, aruggedized probe interface and long (up to three meters)interconnection cables.29.9 MPLAB ICD 3 In-Circuit DebuggerSystemMPLAB ICD 3 In-Circuit Debugger System is Microchip'smost cost effective high-speed hardwaredebugger/programmer for Microchip Flash Digital SignalController (DSC) and microcontroller (MCU)devices. It debugs and programs PIC ® Flash microcontrollersand dsPIC ® DSCs with the powerful, yet easyto-usegraphical user interface of MPLAB IntegratedDevelopment Environment (IDE).The MPLAB ICD 3 In-Circuit Debugger probe is connectedto the design engineer's PC using a high-speedUSB 2.0 interface and is connected to the target with aconnector compatible with the MPLAB ICD 2 or MPLABREAL ICE systems (RJ-11). MPLAB ICD 3 supports allMPLAB ICD 2 headers.29.10 PICkit 3 In-Circuit Debugger/Programmer andPICkit 3 Debug ExpressThe MPLAB PICkit 3 allows debugging and programmingof PIC ® and dsPIC ® Flash microcontrollers at amost affordable price point using the powerful graphicaluser interface of the MPLAB Integrated DevelopmentEnvironment (IDE). The MPLAB PICkit 3 is connectedto the design engineer's PC using a full speed USBinterface and can be connected to the target via anMicrochip debug (RJ-11) connector (compatible withMPLAB ICD 3 and MPLAB REAL ICE). The connectoruses two device I/O pins and the reset line to implementin-circuit debugging and In-Circuit Serial Programming.The PICkit 3 Debug Express include the PICkit 3, demoboard and microcontroller, hookup cables and CDROMwith user’s guide, lessons, tutorial, compiler andMPLAB IDE software. 2011 Microchip Technology Inc. Preliminary DS41615A-page 251

PIC12(L)F150129.11 PICkit 2 DevelopmentProgrammer/Debugger andPICkit 2 Debug ExpressThe PICkit 2 Development Programmer/Debugger isa low-cost development tool with an easy to use interfacefor programming and debugging Microchip’s Flashfamilies of microcontrollers. The full featuredWindows ® programming interface supports baseline(PIC10F, PIC12F5xx, PIC16F5xx), midrange(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bitmicrocontrollers, and many Microchip Serial EEPROMproducts. With Microchip’s powerful MPLAB IntegratedDevelopment Environment (IDE) the PICkit 2enables in-circuit debugging on most PIC ® microcontrollers.In-Circuit-Debugging runs, halts and singlesteps the program while the PIC microcontroller isembedded in the application. When halted at a breakpoint,the file registers can be examined and modified.The PICkit 2 Debug Express include the PICkit 2, demoboard and microcontroller, hookup cables and CDROMwith user’s guide, lessons, tutorial, compiler andMPLAB IDE software.29.12 MPLAB PM3 Device ProgrammerThe MPLAB PM3 Device Programmer is a universal,CE compliant device programmer with programmablevoltage verification at VDDMIN and VDDMAX formaximum reliability. It features a large LCD display(128 x 64) for menus and error messages and a modular,detachable socket assembly to support variouspackage types. The ICSP cable assembly is includedas a standard item. In Stand-Alone mode, the MPLABPM3 Device Programmer can read, verify and programPIC devices without a PC connection. It can also setcode protection in this mode. The MPLAB PM3connects to the host PC via an RS-232 or USB cable.The MPLAB PM3 has high-speed communications andoptimized algorithms for quick programming of largememory devices and incorporates an MMC card for filestorage and data applications.29.13 Demonstration/DevelopmentBoards, Evaluation Kits, andStarter KitsA wide variety of demonstration, development andevaluation boards for various PIC MCUs and dsPICDSCs allows quick application development on fully functionalsystems. Most boards include prototyping areas foradding custom circuitry and provide application firmwareand source code for examination and modification.The boards support a variety of features, including LEDs,temperature sensors, switches, speakers, RS-232interfaces, LCD displays, potentiometers and additionalEEPROM memory.The demonstration and development boards can beused in teaching environments, for prototyping customcircuits and for learning about various microcontrollerapplications.In addition to the PICDEM and dsPICDEM demonstration/developmentboard series of circuits, Microchiphas a line of evaluation kits and demonstration softwarefor analog filter design, KEELOQ ® security ICs, CAN,IrDA ® , PowerSmart battery management, SEEVAL ®evaluation system, Sigma-Delta ADC, flow ratesensing, plus many more.Also available are starter kits that contain everythingneeded to experience the specified device. This usuallyincludes a single application and debug capability, allon one board.Check the Microchip web page (www.microchip.com)for the complete list of demonstration, developmentand evaluation kits.DS41615A-page 252 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F150130.0 PACKAGING INFORMATION30.1 Package Marking Information8-Lead PDIP (300 mil)ExampleXXXXXXXXXXXXXNNNYYWW12F1501I/P e3 01711108-Lead SOIC (3.90 mm)ExampleNNN12F1501I/SN1110017Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNNe3Alphanumeric traceability codePb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( e3 )can be found on the outer packaging for this package.Note:In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.* Standard PICmicro ® device marking consists of Microchip part number, year code, week code andtraceability code. For PICmicro device marking beyond this, certain price adders apply. Please checkwith your Microchip Sales Office. For QTP devices, any special marking adders are included in QTPprice. 2011 Microchip Technology Inc. Preliminary DS41615A-page 253

PIC12(L)F1501Package Marking Information (Continued)8-Lead MSOP (3x3 mm)ExampleF1501I1100178-Lead DFN (2x3x0.9 mm)ExampleBAK110108-Lead DFN (3x3x0.9 mm)XXXXYYWWNNNExampleMFB11110017PIN 1 PIN 1DS41615A-page 254 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501TABLE 30-1:Part NumberPIC12F1501-E/MCPIC12F1501-I/MCPIC12LF1501-E/MCPIC12LF1501-I/MCTABLE 30-2:Part NumberPIC12F1501-E/MFPIC12F1501-I/MFPIC12LF1501-E/MFPIC12LF1501-I/MF8-LEAD 2x3 DFN (MC) TOPMARKINGMarkingBAKBALBAMBAP8-LEAD 3x3 QFN (MF) TOPMARKINGMarkingMFA1MFB1MFC1MFD1 2011 Microchip Technology Inc. Preliminary DS41615A-page 255

PIC12(L)F150130.2 Package DetailsThe following sections give the technical details of the packages.NNOTE 1E11 2 3DEAA2A1Lcb1beeB DS41615A-page 256 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501Note:For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packaging 2011 Microchip Technology Inc. Preliminary DS41615A-page 257

PIC12(L)F1501Note:For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packagingDS41615A-page 258 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501 2011 Microchip Technology Inc. Preliminary DS41615A-page 259

PIC12(L)F1501DNE1ENOTE 11 2ebAA2cφA1L1L DS41615A-page 260 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501Note:For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packaging 2011 Microchip Technology Inc. Preliminary DS41615A-page 261

PIC12(L)F1501NDLbeNKEE2EXPOSED PADNOTE 11 22 1NOTE 1D2TOP VIEWBOTTOM VIEWAA3A1NOTE 2 DS41615A-page 262 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501Note:For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packaging 2011 Microchip Technology Inc. Preliminary DS41615A-page 263

PIC12(L)F1501Note:For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packagingDS41615A-page 264 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501Note:For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packaging 2011 Microchip Technology Inc. Preliminary DS41615A-page 265

PIC12(L)F1501Note:For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packagingDS41615A-page 266 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501APPENDIX A:DATA SHEETREVISION HISTORYRevision AOriginal release (11/2011). 2011 Microchip Technology Inc. Preliminary DS41615A-page 267

PIC12(L)F1501NOTES:DS41615A-page 268 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501INDEXAA/DSpecifications.................................................... 242, 243Absolute Maximum Ratings .............................................. 225AC CharacteristicsIndustrial and Extended ............................................ 238Load Conditions ........................................................ 237ADC .................................................................................. 113Acquisition Requirements ......................................... 124Associated registers.................................................. 126Block Diagram........................................................... 113Calculating Acquisition Time..................................... 124Channel Selection..................................................... 114Configuration............................................................. 114Configuring Interrupt ................................................. 118Conversion Clock...................................................... 114Conversion Procedure .............................................. 118Internal Sampling Switch (RSS) Impedance.............. 124Interrupts................................................................... 116Operation .................................................................. 117Operation During Sleep ............................................ 117Port Configuration ..................................................... 114Reference Voltage (VREF)......................................... 114Source Impedance.................................................... 124Starting an A/D Conversion ...................................... 116ADCON0 Register....................................................... 25, 119ADCON1 Register....................................................... 25, 120ADCON2 Register............................................................. 121ADDFSR ........................................................................... 215ADDWFC .......................................................................... 215ADRESH Register............................................................... 25ADRESH Register (ADFM = 0) ......................................... 122ADRESH Register (ADFM = 1) ......................................... 123ADRESL Register (ADFM = 0).......................................... 122ADRESL Register (ADFM = 1).......................................... 123Alternate Pin Function....................................................... 100Analog-to-Digital Converter. See ADCANSELA Register ............................................................. 103APFCON Register............................................................. 100AssemblerMPASM Assembler................................................... 250Automatic Context Saving................................................... 65BBank 10............................................................................... 28Bank 11............................................................................... 28Bank 12............................................................................... 28Bank 13............................................................................... 28Bank 14-29.......................................................................... 28Bank 2................................................................................. 26Bank 3................................................................................. 26Bank 30............................................................................... 29Bank 4................................................................................. 27Bank 5................................................................................. 27Bank 6................................................................................. 27Bank 7................................................................................. 27Bank 8................................................................................. 27Bank 9................................................................................. 27Block DiagramsADC .......................................................................... 113ADC Transfer Function ............................................. 125Analog Input Model ........................................... 125, 136Clock Source............................................................... 45Comparator............................................................... 132Digital-to-Analog Converter (DAC) ........................... 128Generic I/O Port.......................................................... 99Interrupt Logic............................................................. 61NCO.......................................................................... 184On-Chip Reset Circuit................................................. 53PIC12(L)F1501 ....................................................... 5, 10PWM......................................................................... 161Timer0 ...................................................................... 141Timer1 ...................................................................... 145Timer1 Gate.............................................. 150, 151, 152Timer2 ...................................................................... 157Voltage Reference.................................................... 109Voltage Reference Output Buffer Example .............. 128BORCON Register.............................................................. 55BRA .................................................................................. 216Brown-out Reset (BOR)...................................................... 55Specifications ........................................................... 241Timing and Characteristics ....................................... 240CC CompilersMPLAB C18.............................................................. 250CALL................................................................................. 217CALLW ............................................................................. 217CLCDATA Register........................................................... 181CLCxCON Register .......................................................... 173CLCxGLS0 Register ......................................................... 177CLCxGLS1 Register ......................................................... 178CLCxGLS2 Register ......................................................... 179CLCxGLS3 Register ......................................................... 180CLCxPOL Register ........................................................... 174CLCxSEL0 Register.......................................................... 175Clock SourcesExternal Modes........................................................... 46EC ...................................................................... 46Internal Modes............................................................ 47HFINTOSC ......................................................... 47Internal Oscillator Clock Switch Timing .............. 48LFINTOSC.......................................................... 47Clock Switching .................................................................. 50CMOUT Register .............................................................. 138CMxCON0 Register.......................................................... 137CMxCON1 Register.......................................................... 138Code ExamplesA/D Conversion ........................................................ 118Initializing PORTA ...................................................... 99Writing to Flash Program Memory.............................. 92ComparatorAssociated Registers................................................ 139Operation.................................................................. 131Comparator Module.......................................................... 131Cx Output State Versus Input Conditions................. 133Comparator Specifications................................................ 245ComparatorsC2OUT as T1 Gate................................................... 147Complementary Waveform Generator (CWG).......... 193, 194CONFIG1 Register ............................................................. 40CONFIG2 Register ............................................................. 41Core Function Register....................................................... 24Customer Change Notification Service............................. 275Customer Notification Service .......................................... 275Customer Support............................................................. 275CWG 2011 Microchip Technology Inc. Preliminary DS41615A-page 269

PIC12(L)F1501Auto-shutdown Control ............................................. 200Clock Source............................................................. 196Output Control........................................................... 196Selectable Input Sources .......................................... 196CWGxCON0 Register ....................................................... 203CWGxCON1 Register ....................................................... 204CWGxCON2 Register ....................................................... 205CWGxDBF Register .......................................................... 206CWGxDBR Register.......................................................... 206DDACCON0 (Digital-to-Analog Converter Control 0)Register..................................................................... 130DACCON1 (Digital-to-Analog Converter Control 1)Register..................................................................... 130Data Memory....................................................................... 17DC and AC Characteristics ............................................... 247DC CharacteristicsExtended and Industrial ............................................ 234Industrial and Extended ............................................ 227Development Support ....................................................... 249Device Configuration........................................................... 39Code Protection .......................................................... 42Configuration Word .....................................................39User ID.................................................................. 42, 43Device ID Register .............................................................. 43Device Overview ............................................................. 9, 79Digital-to-Analog Converter (DAC).................................... 127Associated Registers ................................................ 130Effects of a Reset...................................................... 128Specifications............................................................ 245EEffects of ResetPWM mode ............................................................... 163Electrical Specifications .................................................... 225Enhanced Mid-Range CPU................................................. 13Errata .................................................................................... 7Extended Instruction SetADDFSR ................................................................... 215FFirmware Instructions........................................................ 211Fixed Voltage Reference (FVR) ........................................ 109Associated Registers ................................................ 110Flash Program Memory....................................................... 83Associated Registers .................................................. 98Configuration Word w/ Flash Program Memory.......... 98Erasing........................................................................87Modifying..................................................................... 93Write Verify ................................................................. 95Writing......................................................................... 89Flash Program Memory Control .......................................... 83FSR Register....................................................................... 24FVRCON (Fixed Voltage Reference Control) Register ..... 110IINDF Register ..................................................................... 24Indirect Addressing ............................................................. 34Instruction Format ............................................................. 212Instruction Set ................................................................... 211ADDLW ..................................................................... 215ADDWF..................................................................... 215ADDWFC .................................................................. 215ANDLW ..................................................................... 215ANDWF..................................................................... 215BRA .......................................................................... 216CALL......................................................................... 217CALLW ..................................................................... 217LSLF ......................................................................... 219LSRF ........................................................................ 219MOVF ....................................................................... 219MOVIW ..................................................................... 220MOVLB ..................................................................... 220MOVWI ..................................................................... 221OPTION.................................................................... 221RESET...................................................................... 221SUBWFB .................................................................. 223TRIS ......................................................................... 224BCF .......................................................................... 216BSF........................................................................... 216BTFSC...................................................................... 216BTFSS ...................................................................... 216CALL......................................................................... 217CLRF ........................................................................ 217CLRW ....................................................................... 217CLRWDT .................................................................. 217COMF ....................................................................... 217DECF........................................................................ 217DECFSZ ................................................................... 218GOTO ....................................................................... 218INCF ......................................................................... 218INCFSZ..................................................................... 218IORLW...................................................................... 218IORWF...................................................................... 218MOVLW .................................................................... 220MOVWF.................................................................... 220NOP.......................................................................... 221RETFIE..................................................................... 222RETLW ..................................................................... 222RETURN................................................................... 222RLF........................................................................... 222RRF .......................................................................... 223SLEEP ...................................................................... 223SUBLW..................................................................... 223SUBWF..................................................................... 223SWAPF..................................................................... 224XORLW .................................................................... 224XORWF .................................................................... 224INTCON Register................................................................ 66Internal Oscillator BlockINTOSCSpecifications ................................................... 238Internal Sampling Switch (RSS) Impedance...................... 124Internet Address ............................................................... 275Interrupt-On-Change......................................................... 105Associated Registers................................................ 108Interrupts............................................................................. 61ADC .......................................................................... 118Associated registers w/ Interrupts............................... 73TMR1........................................................................ 149INTOSC Specifications ..................................................... 238IOCAF Register ................................................................ 107IOCAN Register ................................................................ 107IOCAP Register ................................................................ 107LLATA Register .................................................................. 103Load Conditions................................................................ 237LSLF ................................................................................. 219LSRF................................................................................. 219DS41615A-page 270 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501MMCLR.................................................................................. 56Internal ........................................................................ 56Memory Organization.......................................................... 15Data ............................................................................ 17Program ...................................................................... 15Microchip Internet Web Site.............................................. 275MOVIW ............................................................................. 220MOVLB ............................................................................. 220MOVWI ............................................................................. 221MPLAB ASM30 Assembler, Linker, Librarian ................... 250MPLAB Integrated Development Environment Software .. 249MPLAB PM3 Device Programmer .................................... 252MPLAB REAL ICE In-Circuit Emulator System................. 251MPLINK Object Linker/MPLIB Object Librarian ................ 250NNCOAssociated registers.................................................. 192NCOxACCH Register........................................................ 190NCOxACCL Register ........................................................ 190NCOxACCU Register........................................................ 190NCOxCLK Register........................................................... 189NCOxCON Register.......................................................... 189NCOxINCH Register ......................................................... 191NCOxINCL Register.......................................................... 191Numerically Controlled Oscillator (NCO)........................... 183OOPCODE Field Descriptions............................................. 211OPTION ............................................................................ 221OPTION Register.............................................................. 143OSCCON Register.............................................................. 51OscillatorAssociated Registers .................................................. 52Associated registers.................................................. 207Oscillator Module ................................................................ 45ECH ............................................................................ 45ECL ............................................................................. 45ECM ............................................................................ 45INTOSC ...................................................................... 45Oscillator Parameters ....................................................... 238Oscillator Specifications.................................................... 238Oscillator Start-up Timer (OST)Specifications............................................................ 241OSCSTAT Register............................................................. 52PPackaging ......................................................................... 253Marking ............................................................. 253, 254PDIP Details.............................................................. 255PCL and PCLATH............................................................... 14PCL Register....................................................................... 24PCLATH Register ............................................................... 24PCON Register ............................................................. 25, 59PIE1 Register................................................................ 25, 67PIE2 Register................................................................ 25, 68PIE3 Register................................................................ 25, 69PIR1 Register................................................................ 25, 70PIR2 Register................................................................ 25, 71PIR3 Register................................................................ 25, 72PMADR Registers............................................................... 83PMADRH Registers ............................................................ 83PMADRL Register............................................................... 96PMADRL Registers............................................................. 83PMCON1 Register........................................................ 83, 97PMCON2 Register........................................................ 83, 98PMDATH Register .............................................................. 96PMDATL Register............................................................... 96PMDRH Register ................................................................ 96PORTA ............................................................................. 101ANSELA Register ..................................................... 101Associated Registers................................................ 104LATA Register ............................................................ 26PORTA Register......................................................... 25Specifications ........................................................... 239PORTA Register............................................................... 102Power-Down Mode (Sleep)................................................. 75Associated Registers.................................................. 78Power-on Reset.................................................................. 54Power-up Time-out Sequence............................................ 56Power-up Timer (PWRT) .................................................... 54Specifications ........................................................... 241PR2 Register ...................................................................... 25Program Memory................................................................ 15Map and Stack (PIC12(L)F1501................................. 16Programming, Device Instructions.................................... 211Pulse Width Modulation (PWM)........................................ 161Associated registers w/ PWM................................... 166PWM ModeDuty Cycle ........................................................ 162Effects of Reset ................................................ 163Example PWM Frequencies andResolutions, 20 MHZ................................ 163Example PWM Frequencies andResolutions, 8 MHz .................................. 163Operation in Sleep Mode.................................. 163Setup for Operation using PWMx pins ............. 164System Clock Frequency Changes .................. 163PWM Period ............................................................. 162Setup for PWM Operation using PWMx Pins ........... 164PWMxCON Register......................................................... 165PWMxDCH Register......................................................... 166PWMxDCL Register.......................................................... 166RReader Response............................................................. 276Read-Modify-Write Operations ......................................... 211RegistersADCON0 (ADC Control 0) ........................................ 119ADCON1 (ADC Control 1) ........................................ 120ADCON2 (ADC Control 2) ........................................ 121ADRESH (ADC Result High) with ADFM = 0) .......... 122ADRESH (ADC Result High) with ADFM = 1) .......... 123ADRESL (ADC Result Low) with ADFM = 0)............ 122ADRESL (ADC Result Low) with ADFM = 1)............ 123ANSELA (PORTA Analog Select) ............................ 103APFCON (Alternate Pin Function Control) ............... 100BORCON Brown-out Reset Control) .......................... 55CLCDATA (Data Output) .......................................... 181CLCxCON (CLCx Control)........................................ 173CLCxGLS0 (Gate 1 Logic Select)............................. 177CLCxGLS1 (Gate 2 Logic Select)............................. 178CLCxGLS2 (Gate 3 Logic Select)............................. 179CLCxGLS3 (Gate 4 Logic Select)............................. 180CLCxPOL (Signal Polarity Control) .......................... 174CLCxSEL0 (Multiplexer Data 1 and 2 Select) .......... 175CMOUT (Comparator Output) .................................. 138CMxCON0 (Cx Control)............................................ 137CMxCON1 (Cx Control 1)......................................... 138Configuration Word 1.................................................. 40 2011 Microchip Technology Inc. Preliminary DS41615A-page 271

PIC12(L)F1501Configuration Word 2 .................................................. 41Core Function, Summary ............................................ 24CWGxCON0 (CWG Control 0).................................. 203CWGxCON1 (CWG Control 1).................................. 204CWGxCON2 (CWG Control 1).................................. 205CWGxDBF (CWGx Dead Band Falling Count) ......... 206CWGxDBR (CWGx Dead Band Rising Count) ......... 206DACCON0 ................................................................ 130DACCON1 ................................................................ 130Device ID .................................................................... 43FVRCON................................................................... 110INTCON (Interrupt Control)......................................... 66IOCAF (Interrupt-on-Change PORTA Flag).............. 107IOCAN (Interrupt-on-Change PORTANegative Edge) ................................................. 107IOCAP (Interrupt-on-Change PORTAPositive Edge)................................................... 107LATA (Data Latch PORTA)....................................... 103NCOxACCH (NCOx Accumulator High Byte) ........... 190NCOxACCL (NCOx Accumulator Low Byte)............. 190NCOxACCU (NCOx Accumulator Upper Byte)......... 190NCOxCLK (NCOx Clock Control) ............................. 189NCOxCON (NCOx Control) ...................................... 189NCOxINCH (NCOx Increment High Byte)................. 191NCOxINCL (NCOx Increment Low Byte) .................. 191OPTION_REG (OPTION) ......................................... 143OSCCON (Oscillator Control) ..................................... 51OSCSTAT (Oscillator Status) ..................................... 52PCON (Power Control Register) ................................. 59PCON (Power Control) ............................................... 59PIE1 (Peripheral Interrupt Enable 1)........................... 67PIE2 (Peripheral Interrupt Enable 2)........................... 68PIE3 (Peripheral Interrupt Enable 3)........................... 69PIR1 (Peripheral Interrupt Register 1) ........................ 70PIR2 (Peripheral Interrupt Request 2) ........................ 71PIR3 (Peripheral Interrupt Request 3) ........................ 72PMADRL (Program Memory Address)........................ 96PMCON1 (Program Memory Control 1)...................... 97PMCON2 (Program Memory Control 2)...................... 98PMDATH (Program Memory Data) ............................. 96PMDATL (Program Memory Data)..............................96PMDRH (Program Memory Address).......................... 96PORTA......................................................................102PWMxCON (PWM Control)....................................... 165PWMxDCH (PWM Control)....................................... 166PWMxDCL (PWM Control) ....................................... 166Special Function, Summary ........................................ 25STATUS......................................................................18T1CON (Timer1 Control)........................................... 153T1GCON (Timer1 Gate Control) ............................... 154T2CON......................................................................159TRISA (Tri-State PORTA)......................................... 102VREGCON (Voltage Regulator Control) ..................... 78WDTCON (Watchdog Timer Control).......................... 81WPUA (Weak Pull-up PORTA) ................................. 104RESET .............................................................................. 221Reset................................................................................... 53Reset Instruction ................................................................. 56Resets................................................................................. 53Associated Registers .................................................. 60Revision History ................................................................ 267SSoftware Simulator (MPLAB SIM)..................................... 251Special Function Registers (SFRs) ..................................... 25Stack ................................................................................... 32Accessing ................................................................... 32Reset .......................................................................... 34Stack Overflow/Underflow .................................................. 56STATUS Register ............................................................... 18SUBWFB .......................................................................... 223TT1CON Register ......................................................... 25, 153T1GCON Register ............................................................ 154T2CON (Timer2) Register................................................. 159T2CON Register ................................................................. 25Temperature IndicatorAssociated Registers................................................ 112Temperature Indicator Module.......................................... 111Thermal Considerations.................................................... 236Timer0............................................................................... 141Associated Registers................................................ 143Operation.................................................................. 141Specifications ........................................................... 242Timer1............................................................................... 145Associated registers ......................................... 155, 207Asynchronous Counter Mode ................................... 147Reading and Writing ......................................... 147Clock Source Selection............................................. 146Interrupt .................................................................... 149Operation.................................................................. 146Operation During Sleep ............................................ 149Prescaler .................................................................. 147Specifications ........................................................... 242Timer1 GateSelecting Source .............................................. 147TMR1H Register....................................................... 145TMR1L Register........................................................ 145Timer2............................................................................... 157Associated registers ................................................. 160TimersTimer1T1CON ............................................................. 153T1GCON........................................................... 154Timer2T2CON ............................................................. 159Timing DiagramsA/D Conversion......................................................... 243A/D Conversion (Sleep Mode).................................. 244Brown-out Reset (BOR)............................................ 240Brown-out Reset Situations ........................................ 55CLKOUT and I/O ...................................................... 239Clock Timing............................................................. 238Comparator Output................................................... 131INT Pin Interrupt ......................................................... 64Internal Oscillator Switch Timing ................................ 49Reset Start-up Sequence ........................................... 57Reset, WDT, OST and Power-up Timer ................... 240Timer0 and Timer1 External Clock ........................... 241Timer1 Incrementing Edge ....................................... 149Wake-up from Interrupt............................................... 76Timing Parameter Symbology .......................................... 237TMR0 Register.................................................................... 25TMR1H Register ................................................................. 25TMR1L Register.................................................................. 25TMR2 Register.................................................................... 25TRIS.................................................................................. 224TRISA Register........................................................... 25, 102DS41615A-page 272 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501VVREF. SEE ADC Reference VoltageVREGCON Register ........................................................... 78WWake-up Using Interrupts ................................................... 75Watchdog Timer (WDT) ...................................................... 56Associated Registers .................................................. 82Modes ......................................................................... 80Specifications............................................................ 241WDTCON Register ............................................................. 81WPUA Register................................................................. 104Write Protection .................................................................. 42WWW Address.................................................................. 275WWW, On-Line Support ....................................................... 7 2011 Microchip Technology Inc. Preliminary DS41615A-page 273

PIC12(L)F1501NOTES:DS41615A-page 274 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501THE MICROCHIP WEB SITEMicrochip provides online support via our WWW site atwww.microchip.com. This web site is used as a meansto make files and information easily available tocustomers. Accessible by using your favorite Internetbrowser, the web site contains the followinginformation:• Product Support – Data sheets and errata,application notes and sample programs, designresources, user’s guides and hardware supportdocuments, latest software releases and archivedsoftware• General Technical Support – Frequently AskedQuestions (FAQ), technical support requests,online discussion groups, Microchip consultantprogram member listing• Business of Microchip – Product selector andordering guides, latest Microchip press releases,listing of seminars and events, listings ofMicrochip sales offices, distributors and factoryrepresentativesCUSTOMER SUPPORTUsers of Microchip products can receive assistancethrough several channels:• Distributor or Representative• Local Sales Office• Field Application Engineer (FAE)• Technical Support• Development Systems Information LineCustomers should contact their distributor,representative or field application engineer (FAE) forsupport. Local sales offices are also available to helpcustomers. A listing of sales offices and locations isincluded in the back of this document.Technical support is available through the web siteat: http://microchip.com/supportCUSTOMER CHANGE NOTIFICATIONSERVICEMicrochip’s customer notification service helps keepcustomers current on Microchip products. Subscriberswill receive e-mail notification whenever there arechanges, updates, revisions or errata related to aspecified product family or development tool of interest.To register, access the Microchip web site atwww.microchip.com. Under “Support”, click on“Customer Change Notification” and follow theregistration instructions. 2011 Microchip Technology Inc. Preliminary DS41615A-page 275

PIC12(L)F1501READER RESPONSEIt is our intention to provide you with the best documentation possible to ensure successful use of your Microchipproduct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which ourdocumentation can better serve you, please FAX your comments to the Technical Publications Manager at(480) 792-4150.Please list the following information, and use this outline to provide us with your comments about this document.TO:RE:Technical Publications ManagerReader ResponseTotal Pages Sent ________From: NameCompanyAddressCity / State / ZIP / CountryTelephone: (_______) _________ - _________Application (optional):Would you like a reply? Y NFAX: (______) _________ - _________Device:PIC12(L)F1501Literature Number:DS41615AQuestions:1. What are the best features of this document?2. How does this document meet your hardware and software development needs?3. Do you find the organization of this document easy to follow? If not, why?4. What additions to the document do you think would enhance the structure and subject?5. What deletions from the document could be made without affecting the overall usefulness?6. Is there any incorrect or misleading information (what and where)?7. How would you improve this document?DS41615A-page 276 Preliminary 2011 Microchip Technology Inc.

PIC12(L)F1501PRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.Device:PART NO. [X] (1) - X /XX XXXDeviceTape and ReelOption:Tape and ReelOptionTemperatureRangePIC12F1501, PIC12LF1501PackageBlank = Standard packaging (tube or tray)T = Tape and Reel (1)PatternExamples:a) PIC12LF1501T - I/SNTape and Reel,Industrial temperature,SOIC packageb) PIC12F1501 - I/PIndustrial temperaturePDIP packagec) PIC12F1501 - E/MFExtended temperature,DFN packageTemperatureRange:I = -40C to +85C (Industrial)E = -40C to +125C (Extended)Package: MC = Micro Lead Frame (DFN) 2x3MF = Micro Lead Frame (DFN) 3x3MS = MSOPP = Plastic DIPSN = SOICPattern:QTP, SQTP, Code or Special Requirements(blank otherwise)Note 1:Tape and Reel identifier only appears in thecatalog part number description. Thisidentifier is used for ordering purposes and isnot printed on the device package. Checkwith your Microchip Sales Office for packageavailability with the Tape and Reel option. 2011 Microchip Technology Inc. Preliminary DS41615A-page 277

Worldwide Sales and ServiceAMERICASCorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200Fax: 480-792-7277Technical Support:http://www.microchip.com/supportWeb Address:www.microchip.comAtlantaDuluth, GATel: 678-957-9614Fax: 678-957-1455BostonWestborough, MATel: 774-760-0087Fax: 774-760-0088ChicagoItasca, ILTel: 630-285-0071Fax: 630-285-0075ClevelandIndependence, OHTel: 216-447-0464Fax: 216-447-0643DallasAddison, TXTel: 972-818-7423Fax: 972-818-2924DetroitFarmington Hills, MITel: 248-538-2250Fax: 248-538-2260IndianapolisNoblesville, INTel: 317-773-8323Fax: 317-773-5453Los AngelesMission Viejo, CATel: 949-462-9523Fax: 949-462-9608Santa ClaraSanta Clara, CATel: 408-961-6444Fax: 408-961-6445TorontoMississauga, Ontario,CanadaTel: 905-673-0699Fax: 905-673-6509ASIA/PACIFICAsia Pacific OfficeSuites 3707-14, 37th FloorTower 6, The GatewayHarbour City, KowloonHong KongTel: 852-2401-1200Fax: 852-2401-3431Australia - SydneyTel: 61-2-9868-6733Fax: 61-2-9868-6755China - BeijingTel: 86-10-8569-7000Fax: 86-10-8528-2104China - ChengduTel: 86-28-8665-5511Fax: 86-28-8665-7889China - ChongqingTel: 86-23-8980-9588Fax: 86-23-8980-9500China - HangzhouTel: 86-571-2819-3187Fax: 86-571-2819-3189China - Hong Kong SARTel: 852-2401-1200Fax: 852-2401-3431China - NanjingTel: 86-25-8473-2460Fax: 86-25-8473-2470China - QingdaoTel: 86-532-8502-7355Fax: 86-532-8502-7205China - ShanghaiTel: 86-21-5407-5533Fax: 86-21-5407-5066China - ShenyangTel: 86-24-2334-2829Fax: 86-24-2334-2393China - ShenzhenTel: 86-755-8203-2660Fax: 86-755-8203-1760China - WuhanTel: 86-27-5980-5300Fax: 86-27-5980-5118China - XianTel: 86-29-8833-7252Fax: 86-29-8833-7256China - XiamenTel: 86-592-2388138Fax: 86-592-2388130ASIA/PACIFICIndia - BangaloreTel: 91-80-3090-4444Fax: 91-80-3090-4123India - New DelhiTel: 91-11-4160-8631Fax: 91-11-4160-8632India - PuneTel: 91-20-2566-1512Fax: 91-20-2566-1513Japan - YokohamaTel: 81-45-471- 6166Fax: 81-45-471-6122Korea - DaeguTel: 82-53-744-4301Fax: 82-53-744-4302Korea - SeoulTel: 82-2-554-7200Fax: 82-2-558-5932 or82-2-558-5934Malaysia - Kuala LumpurTel: 60-3-6201-9857Fax: 60-3-6201-9859Malaysia - PenangTel: 60-4-227-8870Fax: 60-4-227-4068Philippines - ManilaTel: 63-2-634-9065Fax: 63-2-634-9069SingaporeTel: 65-6334-8870Fax: 65-6334-8850Taiwan - Hsin ChuTel: 886-3-5778-366Fax: 886-3-5770-955Taiwan - KaohsiungTel: 886-7-536-4818Fax: 886-7-330-9305Taiwan - TaipeiTel: 886-2-2500-6610Fax: 886-2-2508-0102Thailand - BangkokTel: 66-2-694-1351Fax: 66-2-694-1350EUROPEAustria - WelsTel: 43-7242-2244-39Fax: 43-7242-2244-393Denmark - CopenhagenTel: 45-4450-2828Fax: 45-4485-2829France - ParisTel: 33-1-69-53-63-20Fax: 33-1-69-30-90-79Germany - MunichTel: 49-89-627-144-0Fax: 49-89-627-144-44Italy - MilanTel: 39-0331-742611Fax: 39-0331-466781Netherlands - DrunenTel: 31-416-690399Fax: 31-416-690340Spain - MadridTel: 34-91-708-08-90Fax: 34-91-708-08-91UK - WokinghamTel: 44-118-921-5869Fax: 44-118-921-5820China - ZhuhaiTel: 86-756-3210040Fax: 86-756-321004908/02/11DS41615A-page 278 Preliminary 2011 Microchip Technology Inc.