Manufacturing and Reliability Challenges With QFN - DfR Solutions

Manufacturing and ReliabilityChallenges With QFNDr. Craig Hillman and Cheryl TulkoffDfR SolutionsSMTA/iMAPS Boston, MA April 21, 2009

Who is DfR Solutions? We use Physics- of- Failure(PoF) and Best Practicesexpertise to provide knowledgebasedstrategic quality andreliability solutions to theelectronics industryTechnology InsertionDesignManufacturing and Supplier SelectionProduct Validation and Accelerated TestingRoot-Cause Failure Analysis & Forensics EngineeringUnique combination of expert consultants and state-ofthe-artlaboratory facilities© 2004 - 20092

DfR ActivitiesMeanServicelife, yrs.1000100101.00.1Technology InsertionReliabilityGapTechnology0.5 µm 0.25 µm 130 nm 65 nm 25 nmPb-FreeTransition1995 2005 2015Year producedSupply Chain / ManufacturingAirplanesTelecomMedicalComputerslaptop/palmcell phonesProductTestingDesign ReviewsRoot-CauseAnalysis© 2004 - 20093

Who Uses DfR?Military / Avionics / SpaceLockheed MartinNorthrop GrummanGeneral DynamicsBAE SystemsHoneywellHamilton SundstrandThales CommunicationsRockwell CollinsPortablesLG ElectronicsKyoceraContract ManufacturersFlextronicsBenchmark ElectronicsGold Circuit Electronics (Taiwan)Daeduck (Korea)Viasystems (China)Enterprise / Telecom / ATECisco SystemsHuawei (China)Sun MicrosystemsMotorolaAlcatel-LucentJuniper NetworksKLA-TencorAuto / TransportationGeneral MotorsCaterpillarPanasonic AutomotiveTRW (England)MagnaTakata (Japan)MaterialsGraftechNihon Superior (Japan)Consumer / Appliance Industrial / PowerDell Computers General ElectricHewlett Packard SiemensAppleEmerson ElectricFujitsu (Japan)SchlumbergerSamsung (Korea) Ingersoll RandLG Electronics (Korea) Danaher MotionMicrosoftOlympusXeroxTyco ElectronicsComponentsMedicalSamsung (Korea) Philips MedicalFairchild Semiconductor MedtronicInternational Rectifier GuidantNvidiaCardinal HealthAmphenolBeckman CoulterNICBiotronikCameron HealthCardiac ScienceAnd Many More….© 2004 - 20094

Our LocationsMinneapolis OfficeRandy Schuellerrschueller@dfrsolutions.comMichigan OfficeJim McLeishjmcleish@dfrsolutions.comMid-Atlantic Representative:T&M Sales (Tom O’Connor)TaipeiOffice(Fall 2009)Bay Area OfficeJohn McNultyjmcnulty@dfrsolutions.comAustin OfficeCheryl Tulkoffctulkoff@dfrsolutions.comCorporate HeadquartersCollege Park, MDaskdfr@dfrsolutions.com© 2004 - 20095

Knowledge and Education (Website)Let your staff learnall day / every dayE-LEARNINGScholarly articlesTechnical white papersCase studiesReliability calculatorsOnline presentationsUpdated Website (Launched Aug ’08)© 2004 - 20096

QFN as a ‘Next Generation’ TechnologyWhat is ‘Next Generation’ Technology?Materials or designs currentlybeing used, but not widely adopted(especially among hi-rel manufacturers)Carbon nanotubes are not‘Next Generation’Not used in electronic applicationsBall grid array is not‘Next Generation’Widely adopted© 2004 - 20097

Introduction (cont.)Why is knowing about ‘NextGeneration’ Technologiesimportant?These are the technologies thatyou or your supply chain will useto improve your productCheaper, Faster, Stronger,‘Environmentally-Friendly’, etc.And sooner then you think!© 2004 - 20098

Reliability and Next Gen TechnologiesOne of the most common drivers for failure isinappropriate adoption of new technologiesThe path from consumer (high volume, short lifetime) tohigh rel is not always clearObtaining relevant informationcan be difficultInformation is often segmentedFocus on opportunity, not risksCan be especially true forcomponent packagingBGA, flip chip, QFN© 2004 - 20099

Component Packaging Most of us have little influence overcomponent packaging Most devices offer only one or two packagingstyles Why should you care? Poor understanding of component qualificationprocedures Who tests what and why?© 2004 - 200910

Component TestingReliability testing performed by componentmanufacturers is driven by JEDEC JESD22 series (A & B)Focus is almost entirely on die, packaging, and 1 stlevel interconnections (wire bond, solder bump, etc.)Only focus on 2 nd level interconnects (solder joints)is JESD22-B113 Cyclic Bend TestDriven by cell phone industryThey have little interest in thermal cycling or vibration!© 2004 - 200911

2 nd Level Interconnect Reliability IPC has attempted to rectify this throughIPC-9701 Two problems Adopted by OEMs; not by componentmanufacturers Application specific; you have to tell them theapplication (your responsibility, not theirs) The result An increasing incidence of solder wearout in nextgeneration component packaging© 2004 - 200912

Solder Wearout in Next Gen PackagingPerformance Needs Higher frequencies and data transfer rates Lower resistance-capacitance (RC) constants Higher densities More inside less Lower voltage, but higher current Joule heating is I 2 R Has resulted in less robust package designs© 2004 - 200913

Solder Wearout (cont.) Elimination of leaded devices Provides lower RC and higher package densities Reduces complianceCycles to failure-40 to 125C QFP: >10,000 BGA: 3,000 to 8,000CSP / Flip Chip:

Solder Wearout (cont.) Design change: More silicon, less plastic Increases mismatch in coefficient of thermalexpansion (CTE)BOARD LEVEL ASSEMBLY AND RELIABILITYCONSIDERATIONS FOR QFN TYPE PACKAGES,Ahmer Syed and WonJoon Kang, Amkor Technology.© 2004 - 200915

Solder Wearout (cont.) Hotter devices Increases change in temperature (∆T)10000t f = ∆T nn = 2 (SnPb)n = 2.3 (SnNiCu)n = 2.7 (SnAgCu)Characteristic Life (Cycles to Failure)90008000700060005000400030002000100000 50 100 150 200Change in Temperature ( o C)© 2004 - 200916

Industry Response to SJ Wearout?JEDEC Specification body for component manufacturersJEDEC JESD47 Guidelines for new component qualification Requires 2300 cycles of 0 to 100C Testing is often done on thin boards IPC Specification body for electronic OEMs IPC 9701 Recommends 6000 cycles of 0 to 100C Test boards should be similar thickness asactual design© 2004 - 200917

BIG PROBLEMJEDEC requirements are 60% less than IPCTesting on a thin board can extend lifetimes by 2Xto 4XWhat does this mean?The components you buy may only survive500 cycles of 0 to 100CWhat must you do?Components at risk must be subjected to PoF-basedreliability analysis© 2004 - 200918

Quad Flat Pack No-Lead (QFN)© 2004 - 200919

QFN: What is it?Quad Flat Pack No Lead or Quad Flat Non-Leaded‘The poor man’s ball grid array’Also known as Leadframe Chip Scale Package (LF-CSP) MicroLeadFrame (MLF) Others (MLP, LPCC, QLP, HVQFN, etc.)Overmolded leadframe with bond pads exposed on thebottom and arranged alongthe periphery of the packageDeveloped in the early tomid-1990’s by Motorola,Toshiba, Amkor, etc.Standardized by JEDEC/EIAJ inlate-1990’sFastest growing package type© 2004 - 200920

QFN (cont.)Availability 1 x 2 mm (3 leads) to 14 x 14 mm (120 leads) Dual row may increase I/O count to above 150 Expected to dominate lead counts between 8 to 68Obsolescence of QFP and SOP?Numerous package outline versions (JEDEC) MO-196 (1998) Available in two and four-sidedOther variationsSingulated (punched) and sawedSingle row and dual row© 2004 - 200921

QFN Advantages: Size and CostSmaller, lighter and thinner than comparable leadedpackagesAllows for greater functionality per volumeReduces costComponent manufacturers: More ICs per frameOEMs: Reduced board sizeAttempts to limit the footprint of lower I/O deviceshave previously been stymied for cost reasonsBGA materials and process too expensive© 2004 - 200922

Advantages: ManufacturabilitySmall package without placement and solderprinting constraints of fine pitch leaded devicesNo special handling/trays to avoid bent or non planar pinsEasier to place correctly on PCB pads than fine pitchQFPs, TSOPs, etc.Larger pad geometry makes for simpler solder pasteprintingLess prone to bridging defects when proper pad design andstencil apertures are used. Reduced popcorning moisture sensitivity issues –smaller package© 2004 - 200923

Advantages: Thermal PerformanceMore direct thermal path with larger areaDie → Die Attach → Thermal Pad →Solder → Board Bond PadθJa for the QFN is about half of aleaded counterpart (as per JESD-51)Allows for 2X increase in power dissipation© 2004 - 200924

Advantages: InductanceAt higher operating frequencies, inductance of thegold wire and long lead-frame traces will affectperformanceInductance of QFN is half its leaded counterpartbecause it eliminates gullwing leads and shortenswire lengthsPopular forRF Designshttp://ap.pennnet.com/display_article/153955/36/ARTCL/none/none/1/The-back-end-process:-Step-9-QFN-Singulation/© 2004 - 200925

QFN: Why Not? QFN is a ‘next generation’ technology fornon-consumer electronic OEMs due toconcerns with Manufacturability Compatibility with other OEM processes Reliability Acceptance of this package, especially inlong-life, severe environment, high-relapplications, is currently limited as a result© 2004 - 200926

QFN Manufacturability: Bond PadsNon Solder Mask Defined Pads Preferred (NSMD) Copper etch process has tighter process control than solder mask process Makes for more consistent, strong solder joints since solder bonds to both tops andsides of padsUse solder mask defined pads (SMD) with care Can be used to avoid bridging between pads, especially between thermal and signalpads. Pads can grow in size quite a bit based on PCB mfg capabilitiesCan lose solder volume through vias in thermal pads May need to tent, plug, or cap vias to keep sufficient paste volume Tenting and plugging vias is often not well controlled and can lead to placement andchemical entrapment issues Exercise care with devices placed on opposing side of QFN Can create placement issues if solder “bumps” are created in vias Can create solder short conditions on the opposing device Capping is a more robust, more expensive process that eliminates these concerns© 2004 - 200927

Bond Pads (cont.)Extend bond pad 0.2 – 0.3 mm beyondpackage footprintMay or may not solder to cut edgeAllows for better visual inspectionReally need X-ray for best resultsAllows for verification of bridging,adequate solder coverage andvoid percentageNote: Lacking in good criteriafor acceptable voiding© 2004 - 200928

Manufacturability: Stencil DesignStencil thickness and aperture design can be crucial formanufacturabilityExcessive amount of paste can inducefloat, lifting the QFN off the boardExcessive voiding can also be inducedthrough inappropriate stencil designFollow manufacturer’s guidelinesGoal is 2-3 mils of solder thicknessRules of thumb (thermal pad) Ratio of aperture/pad ~0.5:1Consider multiple, smaller apertures(avoid large bricks of solder paste)Reduces propensity for solder balling© 2004 - 200929

Manufacturability: Reflow & MoistureQFN solder joints are more susceptible to dimensional changesCase Study: Military supplier experienced solder separation under QFNQFN supplier admitted that the package was more susceptible tomoisture absorption that initially expected Resulted in transient swelling during reflow soldering Induced vertical lift, causing solder separationWas not popcorning No evidence of cracking or delamination in component package© 2004 - 200930

Manufacturability: QFN Joint InspectionSingulated through sawingSingulated through punchingConcave fillet possible with both sawed or punched QFN Short storage times, active fluxGreater opportunity with punched QFN More copper exposed© 2004 - 200931

Manufacturability: QFN Joint InspectionConvex or absence of fillet highly likelyEtching of leadframe can prevent pad from reaching edgeof packageEdge of bond pad is not plated for solderability© 2004 - 200932

QFN Singulation ProcessSingulated operationTitle: Reliability aspects of electronic devices for advanced requirementsAuthor(s): Florian Schußler, Michael Rosch, Johannes Horber, Klaus FeldmannJournal: Circuit WorldYear: 2008, Volume: 34, Issue: 3, Page: 23 - 30© 2004 - 200933

Title: Reliability study of surface mount printed circuit board assemblies with lead-free solder jointsAuthor(s): Jeffery C.C. Lo, B.F. Jia, Z. Liu, J. Zhu, S.W. Ricky LeeJournal: Soldering & Surface Mount TechnologyYear: 2008, Volume: 20, Issue: 2, Page: 30 - 38© 2004 - 200934

Manufacturability: QFN Joint InspectionA large convex fillet is often an indication of issuesPoor wetting under the QFNTilting due to excessive solder paste under the thermal padElevated solder surface tension, from insufficient solderpaste under the thermal pad, pulling the package down© 2004 - 200935

After a quick review of QFN design differences, I will get to the perimeter solder joint issue.There are several 'flavors' of QFNs. Some QFN leadframes are designed placing the units very close together, providingvery high leadframe utilization. These QFNs are molded in large area blocks with many individual die assemblies embeddedin each molded block. There may be 2 - 5 molded blocks measuring approximately 50x50mm to 70x120mm on eachleadframe strip. In another design, the QFNs are spaced farther apart on the leadframe strip and each QFN is molded in itsown cavity in the large molding tools. The block molded units are singulated after leadframe plating with a diamond dicingsaw, while the individually molded units are singulated with punch tooling. The sawn parts have sharp square edges. Theindividually molded units have tapered sidewalls and a small protrusion from the base of the part around the packageperimeter.With the former, you can see no contacts when viewed from the top, while with the latter you can see the top sides of theindividual contacts around the package perimeter. A further variation in the package design relates to the way the leadframeis etched. It is common to etch 1/2 of the leadframe thickness from the bottom (contact side) in several locations on theleadframe. This is done around the perimeter of the die attach paddle to increase the separation distance between the edgeof the exposed DAP backside and the contact pads while maintaining maximum DAP size on the top surface for die attachand possible wire bond down-bonding around the DAP perimeter. Another area that is 'half-etched' is in the region where theleadframe exits the edge of the package. If the full leadframe thickness is maintained at the site where singulation will occur,the diamond saw must cut through the full 200 micrometer Cu leadframe thickness, or the punch tool must cut through fullthickness. This causes more rapid saw blade wear and can cause higher stress on the edge of the package during punchsingulation.If the full leadframe thickness is maintained, a small solder fillet may form up the thickness of the leadframe if the flux isactive enough and the QFNs are not old and heavily oxidized on the exposed copper surface. If the leadframe is half etchedin this perimeter region, the bottom surface contact pad will not reach the edge of the package, so no fillet will form. Bothdesigns have been proven very reliable since the large exposed DAP is generally soldered to the PCB during boardassembly, relieving much of the temp cycle induced stress in the contact pads.If you do not design the thermal pad on the PCB properly, during SMT the solder on the PCB thermal pad will melt, and wetthe exposed backside of the QFN DAP, and problems may result. The wetting of the DAP will pull the package close to thePCB surface. If the amount of solder on the PCB thermal pad is too small, the solder surface tension/wetting will pull thepackage down and can squeeze the contact pad solder forcing a blob of solder to protrude from the joint, even when theleadframe has been half-etched on the perimeter. This blob can go inward and short to the thermal pad or outward whereyou can see it as a 'solder bubble". If the solder on the PCB thermal pad is too great, during reflow the package can 'float'and cause opens on a package edge. Hope this helps.© 2004 - 200936

Manufacturability: ReworkCan be difficult to replace a package and getadequate soldering of thermal / internal pads.Mini-stencils, preforms, or rebump techniques can be usedto get sufficient solder volumeNot directly accessible with soldering iron and wirePortable preheaters used in conjunction with soldering ironcan simplify small scale repair processesClose proximity with capacitors often requiresadjacent components to be resoldered / replaced aswell© 2004 - 200937

Manufacturability: Board Flexure Area array devices are known to have boardflexure limitations For SAC attachment, maximum microstrain canbe as low as 500 ue QFN has an even lower level of compliance Limited quantifiable knowledge in this area Must be conservative during board build IPC is working on a specification similar to BGAs© 2004 - 200938

Reliability: Thermal CyclingOrder of magnitude reduction in time tofailure from QFP3X reduction from BGADriven by die / package ratio 40% die; tf = 8K cycles (-40 / 125C) 75% die; tf = 800 cycles (-40 / 125C)Driven by size and I/O# 44 I/O; tf = 1500 cycles (-40 / 125C) 56 I/O; tf = 1000 cycles (-40 / 125C)Very dependent upon solder bond withthermal padQFP: >10,000BGA: 3,000 to 8,000QFN: 1,000 to 3,000© 2004 - 200939

Thermal Cycling: Conformal CoatingCare must be taken when using conformal coating over QFNCoating can infiltrate under the QFNSmall standoff height allows coating to cause liftHamilton Sundstrand found a significant reduction in time tofailure (-55 / 125C)Uncoated: 2000 to 2500 cyclesCoated: 300 to 700 cyclesAlso driven by solder jointsensitivity to tensile stressesDamage evolution is farhigher than for shear stressesWrightson, SMTA Pan Pac 2007© 2004 - 200940

Reliability: Bend CyclingLow degree of complianceand large footprint canalso result in issues duringcyclic flexure eventsExample: IR tested a5 x 6mm QFN toJEDEC JESD22-B113 Very low beta (~1)Suggests brittle fracture, possible along the interface© 2004 - 200941

Reliability: Dendritic GrowthLarge area, multi-I/O and low standoff can trap fluxunder the QFNProcesses using no-clean flux should be requalifiedParticular configuration could result in weak organic acidconcentrations above maximum (150 – 200 ug/in 2 )Those processes not using no-clean flux will likelyexperience dendritic growth without modification ofcleaning processChanges in water temperatureChanges in saponifierChanges to impingement jets© 2004 - 200942

Dendritic Growth (cont.)The electric field strength between adjacent conductors is astrong driver for dendritic growth Voltage / distanceDigital technology typically has a maximum field strength of0.5 V/mil TSSOP80 with 3.3VDC power and 16 mil pitchPrevious generation analog / power technology had a maximumfield strength of 1.6 V/mil SOT23 with 50VDC power and 50 mil pitchIntroduction of QFN has resulted in electric fields as high as3.5 V/mil 24VDC and 16 mil pitch© 2004 - 200943

Dendritic Growth (cont.)Some component manufacturers are aware of thisissue and separate power and groundLinear Technologies (left) has strong separation power andgroundIntersil (right) has power and ground on adjacent pins© 2004 - 200944

QFN: Risk MitigationAssess manufacturabilityDegree of reflow profilingControl of board flexureDOE on stencil designDual row QFN is especially difficultAssess reliabilityOwnership of 2 nd level interconnectis often lackingExtrapolate to needed field reliabilitySome companies have reballed QFNto deal with concerns© 2004 - 200945