Mentor Graphics ASIC Design Flow
Mentor Graphics ASIC Design Flow
Mentor Graphics ASIC Design Flow
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VLSI/FPGA<br />
<strong>Design</strong> and Test <strong>Flow</strong> with<br />
<strong>Mentor</strong> <strong>Graphics</strong> CAD Tools<br />
Victor P. Nelson
<strong>Mentor</strong> <strong>Graphics</strong> CAD Tool Suites<br />
�� IC/SoC IC/ SoC design flow 1<br />
�� DFT/BIST/ATPG design flow 1<br />
�� FPGA design flow 2,3<br />
�� PCB design flow 2<br />
�� Digital/analog/mixed-signal Digital/analog/mixed signal modeling & simulation 1,2<br />
�� <strong>ASIC</strong>/FPGA synthesis 1,2<br />
�� Vendor-provided Vendor provided (Xilinx,Altera,etc<br />
( Xilinx,Altera,etc.) .) back end tools 2<br />
1. User-setup User setup selection: eda/mentor/IC<strong>Flow</strong>2006.1<br />
2. User-setup User setup selection: eda/mentor/EN2002.3<br />
3. User-setup User setup selection: eda/mentor/FPGA<br />
eda/mentor/FPGA
<strong>Mentor</strong> <strong>Graphics</strong> CAD Tools<br />
(select “eda eda/mentor /mentor” in user-setup user setup on the Sun network*)<br />
IC<strong>Flow</strong>2006.1–– For For custom custom & & standard standard cell cell IC IC designs designs<br />
– IC flow tools (<strong>Design</strong> (<strong>Design</strong> Architect--IC, Architect IC, IC IC Station, Station, Calibre)) Calibre<br />
– Digital/analog/mixed simulation ((Modelsim,ADVance<br />
– HDL Synthesis (Leonardo) (Leonardo)<br />
– ATPG/DFT/BIST tools (DFT (DFT Advisor, Advisor, Flextest, Flextest,<br />
Fastscan)) Fastscan<br />
– Limited access to Quicksim II (some (some technologies)<br />
technologies)<br />
EN2002u3 –– For For FPGA FPGA ““front front end”” end design design & & printed printed circuit circuit boards boards<br />
– <strong>Design</strong> Architect, Quicksim II, Quicksim Pro (Schematic/Simulation)<br />
– ModelSim & Leonardo (HDL (HDL Simulation/Synthesis)<br />
– Xilinx ISE & Altera “Quartus Quartus” tools (Back (Back end end design) design)<br />
�� IC<strong>Flow</strong>2006.1<br />
�� EN2002u3<br />
FPGA (FPGA (FPGA Advantage, Advantage, Modelsim, Modelsim,<br />
Leonardo) Leonardo)<br />
�� FPGA<br />
Modelsim,ADVance MS,Eldo,MachTA))<br />
MS,Eldo,MachTA<br />
*Only *Only one one of of the the above above three three groups groups may may be be selected selected at at a a time<br />
time
<strong>Mentor</strong> <strong>Graphics</strong> <strong>ASIC</strong> <strong>Design</strong> Kit (ADK)<br />
�� Technology files & standard cell libraries<br />
– AMI: ami12, ami05 (1.2, 0.5 μm) m)<br />
– TSMC: tsmc035, tsmc025, tsmc018 (0.35, 0.25, 0.18 μm) m)<br />
�� IC flow & DFT tool support files:<br />
– Simulation<br />
�� VHDL/Verilog<br />
VHDL/ Verilog/Mixed /Mixed-Signal Signal models ((Modelsim/ADVance<br />
Modelsim/ADVance MS) MS)<br />
�� Analog (SPICE) models ((Eldo/Accusim<br />
Eldo/Accusim))<br />
�� Post-layout Post layout timing (Mach (Mach TA) TA)<br />
�� Digital schematic (Quicksim Quicksim II, II, Quicksim Quicksim Pro) Pro) (exc. tsmc025,tsmc018)<br />
– Synthesis to std. cells ((LeonardoSpectrum<br />
LeonardoSpectrum))<br />
– <strong>Design</strong> for test & ATPG (DFT (DFT Advisor, Advisor, Flextest/Fastscan))<br />
Flextest/Fastscan<br />
– Schematic capture (<strong>Design</strong> (<strong>Design</strong> Architect--IC)<br />
Architect IC)<br />
– IC physical design (standard cell & custom)<br />
�� Floorplan, Floorplan,<br />
place & route (IC (IC Station) Station)<br />
�� <strong>Design</strong> rule check, layout vs schematic, parameter extraction ((Calibre Calibre))
Xilinx/Altera<br />
Xilinx/ Altera FPGA/CPLD <strong>Design</strong><br />
�� Technology files & libraries for front-end front end design with<br />
<strong>Mentor</strong> <strong>Graphics</strong> tools<br />
– Schematic symbols for <strong>Design</strong> <strong>Design</strong> Architect Architect<br />
– Simulation models for Quicksim Quicksim II, II, Quicksim Quicksim Pro Pro<br />
– Synthesis library for Leonardo Leonardo<br />
�� Vendor tools for back-end back end design<br />
(map, place, route, configure, timing)<br />
– Xilinx Integrated Integrated Software Software Environment Environment (ISE)<br />
�� Xilinx XST can synthesize the design from VHDL or Verilog (instead<br />
of Leonardo)<br />
– Altera Quartus Quartus II II & & Max+Plus2<br />
Max+Plus2
DFT/BIST<br />
& ATPG<br />
Test vectors<br />
Standard Cell IC<br />
& FPGA/CPLD<br />
DRC & LVS<br />
Verification<br />
<strong>ASIC</strong> <strong>Design</strong> <strong>Flow</strong><br />
Synthesis<br />
Behavioral<br />
Model<br />
VHDL/Verilog<br />
Gate-Level<br />
Netlist<br />
Transistor-Level<br />
Netlist<br />
Physical<br />
Layout<br />
Map/Place/Route<br />
Full-custom IC<br />
IC Mask Data/FPGA Configuration File<br />
Verify<br />
Function<br />
Verify<br />
Function<br />
Verify Function<br />
& Timing<br />
Verify<br />
Timing
Behavioral <strong>Design</strong> & Verification<br />
VHDL<br />
Verilog<br />
SystemC<br />
(mostly technology-independent)<br />
technology independent)<br />
ModelSim<br />
(digital)<br />
Leonardo<br />
Spectrum<br />
(digital)<br />
Create Behavioral/RTL<br />
HDL Model(s)<br />
Simulate to Verify<br />
Functionality<br />
Synthesize Gate-Level<br />
Circuit<br />
Post-Layout Simulation,<br />
Technology-Specific Netlist<br />
to Back-End Tools<br />
VHDL-AMS<br />
Verilog-A<br />
ADVance MS<br />
(analog/mixed signal)<br />
Technology Libraries
ADVance MS Simulation System<br />
�� ADVance MS “kernel kernel” supports:<br />
– VHDL & Verilog: Verilog:<br />
digital (via ModelSim) ModelSim<br />
– VHDL-AMS VHDL AMS & Verilog-A: Verilog A: analog/mixed signal<br />
– Eldo/SPICE: Eldo/SPICE:<br />
analog (via Eldo) Eldo<br />
– Eldo RF/SPICE: analog RF (via Eldo RF)<br />
– Mach TA/SPICE: high-speed high speed analog/timing<br />
�� Invoke stand-alone stand alone or from <strong>Design</strong> Architect-IC<br />
Architect IC<br />
�� <strong>Mentor</strong> <strong>Graphics</strong> “Legacy Legacy” Simulators<br />
Simulators (PCB design)<br />
– Quicksim II, Quicksim Pro (digital)<br />
– <strong>ASIC</strong>: adk_quicksim<br />
adk_quicksim<br />
– FPGA/PLD: Xilinx: pld_quicksim,<br />
pld_quicksim,<br />
Altera: Altera:<br />
max2_quicksim<br />
– Accusim (analog): adk_accusim<br />
adk_accusim
ADVance MS<br />
Digital, Analog, Mixed-Signal Mixed Signal Simulation<br />
Working<br />
Library<br />
Simulation<br />
Setup<br />
VHDL,Verilog,<br />
VHDL-AMS, Verilog-A,<br />
SPICE Netlists<br />
<strong>Design</strong>_1<br />
<strong>Design</strong>_2<br />
VITAL<br />
ADVance MS<br />
SPICE<br />
models<br />
IEEE 1164 Resource<br />
Libraries<br />
Input<br />
Stimuli<br />
Eldo,<br />
EZwave<br />
Eldo RF or Xelga ModelSim<br />
Analog<br />
(SPICE)<br />
Mach TA<br />
Mach PA<br />
View Results<br />
Digital<br />
(VHDL,Verilog)<br />
Mixed Signal<br />
(VHDL-AMS,<br />
Verilog-A)
Example: 4-bit 4 bit binary counter<br />
�� VHDL model (count4.vhd)<br />
(count4.vhd)<br />
– Create working library: vlib vlib work work<br />
vmap vmap work work work work<br />
– Compile: vcom vcom count4.vhd count4.vhd<br />
– Simulate: vsim vsim count4(rtl) count4(rtl)<br />
�� ModelSim simulation-control simulation control inputs<br />
– ModelSim “Macro<br />
– OR, VHDL testbench<br />
�� ModelSim results<br />
– listing listing or or waveform<br />
waveform<br />
Macro” (count4_rtl.do)
-- count4.vhd 4-bit 4 bit parallel-load parallel load synchronous counter<br />
LIBRARY ieee; ieee<br />
USE ieee.std_logic_1164.all; USE ieee.numeric_std.all;<br />
ieee.numeric_std.all<br />
ENTITY count4 IS<br />
PORT (clock,clear,enable,load_count<br />
( clock,clear,enable,load_count : IN STD_LOGIC;<br />
D: IN unsigned(3 downto 0);<br />
Q: OUT unsigned(3 downto 0));<br />
END count4;<br />
ARCHITECTURE rtl OF count4 IS<br />
SIGNAL int : unsigned(3 downto 0);<br />
BEGIN<br />
PROCESS(clear, PROCESS(clear,<br />
clock, enable)<br />
BEGIN<br />
IF (clear = '1') THEN<br />
int
Test stimulus:<br />
Modelsim “do do” file: count4_rtl.do<br />
add wave /clock /clear /enable /load_count<br />
/ load_count /D /Q<br />
add list /clock /clear /enable /load_count<br />
/ load_count /D /Q<br />
force /clock 0 0, 1 10 -repeat repeat 20<br />
force /clear 0 0, 1 5, 0 10<br />
force /enable 0 0, 1 25<br />
force /load_count<br />
/ load_count 0 0, 1 20, 0 35, 1 330, 0 350<br />
force /D 10#5 0, 10#9 300<br />
run 400
Testbench: Testbench:<br />
count4_bench.vhd<br />
LIBRARY ieee; ieee;<br />
USE ieee.std_logic_1164.all; USE ieee.numeric_std.all;<br />
ieee.numeric_std.all<br />
ENTITY count4_bench is end count4_bench;<br />
ARCHITECTURE test of count4_bench is<br />
component count4<br />
PORT (clock,clear,enable,load_count<br />
( clock,clear,enable,load_count : IN STD_LOGIC;<br />
D: IN unsigned(3 downto 0);<br />
Q: OUT unsigned(3 downto 0));<br />
end component;<br />
for all: count4 use entity work.count4(behavior);<br />
signal clk : STD_LOGIC := '0';<br />
signal clr, clr,<br />
en, ld: STD_LOGIC;<br />
signal din, qout: qout:<br />
unsigned(3 downto 0);<br />
begin<br />
UUT: count4 port map(clk,clr,en,ld,din,qout);<br />
map(clk,clr,en,ld,din,qout);<br />
clk
Count4 – Simulation waveform<br />
Clear<br />
Parallel<br />
Load<br />
Counting
ADVance MS : mixed-signal mixed signal simulation<br />
A/D converter<br />
digital<br />
analog<br />
VHDL-AMS
ADVance MS: mixed Verilog-SPICE<br />
Verilog SPICE<br />
Verilog top<br />
(test bench)<br />
SPICE<br />
subcircuit
Technology<br />
Synthesis<br />
Libraries<br />
FPGA<br />
<strong>ASIC</strong><br />
ADK<br />
AMI 0.5, 1.2<br />
TSMC 0.35, 0.25<br />
Automated Synthesis with<br />
Leonardo Spectrum<br />
Leonardo Spectrum<br />
(Level 3)<br />
Technology-<br />
Specific<br />
Netlist<br />
VHDL, Verilog, SDF,<br />
EDIF, XNF<br />
VHDL/Verilog<br />
Behavioral/RTL Models<br />
<strong>Design</strong><br />
Constraints<br />
Level 1 – FPGA<br />
Level 2 – FPGA + Timing
Leonardo – <strong>ASIC</strong> Synthesis <strong>Flow</strong>
Leonardo synthesis procedure<br />
1. Invoke leonardo leonardo<br />
2. Select & load a technology library (<strong>ASIC</strong> or FPGA)<br />
– <strong>ASIC</strong> <strong>ASIC</strong> > > ADK ADK > > TSMC TSMC 0.35 0.35 micron micron<br />
): count4.vhd count4.vhd<br />
3. Read input VHDL/Verilog<br />
VHDL/ Verilog file(s): file(s<br />
4. Enter any constraints (clock freq, delays, etc.)<br />
5. Optimize for area/delay/effort level<br />
6. Write output file(s) file(s<br />
– count4_0.vhd count4_0.vhd -- VHDL VHDL netlist netlist<br />
– count4.v count4.v -- Verilog Verilog netlist netlist (for (for IC IC layout) layout)<br />
– count4.sdf count4.sdf -- Standard Standard delay delay format format file file (for (for timing) timing)<br />
– count4.edf count4.edf -- EDIF EDIF netlist netlist (for (for Xilinx/Altera<br />
Xilinx/ Altera FPGA)<br />
FPGA)
Leonardo-synthesized<br />
Leonardo synthesized netlist count4_0.vhd<br />
library IEEE; use IEEE.STD_LOGIC_1164.all;<br />
library adk; adk;<br />
use adk.adk_components.all;<br />
adk.adk_components.all;<br />
-- ADDED BY VPN<br />
entity count4 is<br />
port (<br />
clock : IN std_logic ; clear : IN std_logic ; enable : IN std_logic ; load_count : IN std_logic ;<br />
D : IN std_logic_vector (3 DOWNTO 0) ; Q : OUT std_logic_vector (3 DOWNTO 0)) ;<br />
end count4 ;<br />
architecture netlist of count4 is -- rtl changed to netlist by VPN<br />
signal Q_3_EXMPLR, Q_2_EXMPLR, Q_1_EXMPLR, Q_0_EXMPLR, nx8, nx14, nx14,<br />
nx22,<br />
nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx169, nx181,<br />
nx183, nx185, nx187, nx189: std_logic ;<br />
begin<br />
Q(3) clock, R=>clear); R=>clear);<br />
ix127 : mux21_ni port map ( Y=>nx126, A0=>Q_0_EXMPLR, A1=>nx8, A1=>nx8,<br />
S0=>enable );<br />
ix9 : oai21 port map ( Y=>nx8, A0=>load_count<br />
A0=> load_count, , A1=>Q_0_EXMPLR, B0=>nx169 );<br />
ix170 : nand02 port map ( Y=>nx169, A0=>D(0), A1=>load_count<br />
A1=> load_count); );<br />
Q_1_EXMPLR_EXMPLR : dffr port map ( Q=>Q_1_EXMPLR, QB=>OPEN, D=>nx136, CLK=>clock, R=>clear);<br />
ix137 : mux21_ni port map ( Y=>nx136, A0=>Q_1_EXMPLR, A1=>nx28, A1=>nx28,<br />
S0=> enable);<br />
ix29 : ao22 port map ( Y=>nx28, A0=>D(1), A1=>load_count<br />
A1=> load_count, , B0=>nx14, B1=> nx22);<br />
ix15 : or02 port map ( Y=>nx14, A0=>Q_0_EXMPLR, A1=>Q_1_EXMPLR);<br />
A1=>Q_1_EXMPLR);<br />
ix23 : aoi21 port map ( Y=>nx22, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, A1=>Q_0_EXMPLR,<br />
B0=> load_count);<br />
load_count);<br />
Q_2_EXMPLR_EXMPLR : dffr port map ( Q=>Q_2_EXMPLR, QB=>OPEN, D=>nx146, CLK=>clock, R=>clear); R=> clear);<br />
ix147 : mux21_ni port map ( Y=>nx146, A0=>Q_2_EXMPLR, A1=>nx48, A1=>nx48,<br />
S0=> enable);<br />
ix49 : oai21 port map ( Y=>nx48, A0=>nx181, A1=>nx183, B0=>nx189);<br />
B0=> nx189);<br />
ix182 : aoi21 port map ( Y=>nx181, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, A1=>Q_0_EXMPLR,<br />
B0=> Q_2_EXMPLR);<br />
ix184 : nand02 port map ( Y=>nx183, A0=>nx185, A1=>nx187);<br />
ix186 : inv01 port map ( Y=>nx185, A=>load_count<br />
A=> load_count); );<br />
ix188 : nand03 port map ( Y=>nx187, A0=>Q_2_EXMPLR, A1=>Q_1_EXMPLR, A1=>Q_1_EXMPLR,<br />
A2=> Q_0_EXMPLR);<br />
ix190 : nand02 port map ( Y=>nx189, A0=>D(2), A1=>load_count<br />
A1=> load_count); );<br />
Q_3_EXMPLR_EXMPLR : dffr port map ( Q=>Q_3_EXMPLR, QB=>OPEN, D=>nx156, CLK=>clock, R=>clear); R=>clear);<br />
ix157 : mux21_ni port map ( Y=>nx156, A0=>Q_3_EXMPLR, A1=>nx62, A1=>nx62,<br />
S0=> enable);<br />
ix63 : mux21_ni port map ( Y=>nx62, A0=>nx54, A1=>D(3), S0=>load_count<br />
S0= load_count); );<br />
ix55 : xnor2 port map ( Y=>nx54, A0=>Q_3_EXMPLR, A1=>nx187);<br />
A1=>nx187)<br />
end netlist ;
Verilog description for cell count4, LeonardoSpectrum Level 3, 2005a.82<br />
module count4 ( clock, clear, enable, load_count, load_count,<br />
D, Q ) ;<br />
input clock ;<br />
input clear ;<br />
input enable ;<br />
input load_count ;<br />
input [3:0]D ;<br />
output [3:0]Q ;<br />
wire nx8, nx14, nx22, nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx169, nx181, nx183, nx185, nx187,<br />
nx189;<br />
wire [3:0] \$dummy $dummy ;<br />
dffr Q_0__rename_rename (.Q (Q[0]), .QB (\$dummy ( $dummy [0]), .D (nx126), .CLK (clock), .R (clear)) ;<br />
mux21_ni ix127 (.Y (nx126), .A0 (Q[0]), .A1 (nx8), .S0 (enable)) (enable))<br />
;<br />
oai21 ix9 (.Y (nx8), .A0 (load_count<br />
( load_count), ), .A1 (Q[0]), .B0 (nx169)) ;<br />
nand02 ix170 (.Y (nx169), .A0 (D[0]), .A1 (load_count<br />
( load_count)) )) ;<br />
dffr Q_1__rename_rename (.Q (Q[1]), .QB (\$dummy ( $dummy [1]), .D (nx136), .CLK (clock), .R (clear)) ;<br />
mux21_ni ix137 (.Y (nx136), .A0 (Q[1]), .A1 (nx28), .S0 (enable)) (enable))<br />
;<br />
ao22 ix29 (.Y (nx28), .A0 (D[1]), .A1 (load_count<br />
( load_count), ), .B0 (nx14), .B1 (nx22) ) ;<br />
or02 ix15 (.Y (nx14), .A0 (Q[0]), .A1 (Q[1])) ;<br />
aoi21 ix23 (.Y (nx22), .A0 (Q[1]), .A1 (Q[0]), .B0 (load_count<br />
( load_count)) )) ;<br />
dffr Q_2__rename_rename (.Q (Q[2]), .QB (\$dummy ( $dummy [2]), .D (nx146), .CLK (clock), .R (clear)) ;<br />
mux21_ni ix147 (.Y (nx146), .A0 (Q[2]), .A1 (nx48), .S0 (enable)) (enable))<br />
;<br />
oai21 ix49 (.Y (nx48), .A0 (nx181), .A1 (nx183), .B0 (nx189)) (nx189) ) ;<br />
aoi21 ix182 (.Y (nx181), .A0 (Q[1]), .A1 (Q[0]), .B0 (Q[2])) ;<br />
nand02 ix184 (.Y (nx183), .A0 (nx185), .A1 (nx187)) ;<br />
inv01 ix186 (.Y (nx185), .A (load_count<br />
( load_count)) )) ;<br />
nand03 ix188 (.Y (nx187), .A0 (Q[2]), .A1 (Q[1]), .A2 (Q[0])) (Q[0]) ) ;<br />
nand02 ix190 (.Y (nx189), .A0 (D[2]), .A1 (load_count<br />
( load_count)) )) ;<br />
dffr Q_3__rename_rename (.Q (Q[3]), .QB (\$dummy ( $dummy [3]), .D (nx156), .CLK (clock), .R (clear)) ;<br />
mux21_ni ix157 (.Y (nx156), .A0 (Q[3]), .A1 (nx62), .S0 (enable)) (enable))<br />
;<br />
mux21_ni ix63 (.Y (nx62), .A0 (nx54), .A1 (D[3]), .S0 (load_count<br />
( load_count)) )) ;<br />
xnor2 ix55 (.Y (nx54), .A0 (Q[3]), .A1 (nx187)) ;<br />
endmodule
Post-synthesis Post synthesis simulation<br />
(Leonardo Leonardo-generated generated netlist) netlist<br />
�� Verify synthesized netlist matches behavioral<br />
model<br />
�� Create simulation primitives library for std cells:<br />
>>vlib vlib adk adk<br />
>>vcom vcom $ADK/technology/adk.vhd<br />
$ADK/technology/ adk.vhd<br />
>>vcom vcom $ADK/technology/adk_comp.vhd<br />
$ADK/technology/ adk_comp.vhd<br />
�� Insert library/package declaration into netlist<br />
library library adk;; adk<br />
use use adk.adk_components.all;;<br />
adk.adk_components.all<br />
VITAL<br />
models of all<br />
ADK std cells<br />
�� Simulate in Modelsim, Modelsim,<br />
using “do do file” file or test bench from<br />
original behavioral simulation<br />
– results results should should match match
Post-synthesis Post synthesis timing analysis<br />
�� Leonardo can generate SDF (std. delay format) file with<br />
technology-specific, technology specific, VITAL-compliant VITAL compliant timing parameters.<br />
(CELLTYPE "dffr " dffr") ")<br />
(INSTANCE Q_0_EXMPLR_EXMPLR)<br />
(DELAY<br />
(ABSOLUTE<br />
(PORT D (::0.00) (::0.00))<br />
(PORT CLK (::0.00) (::0.00))<br />
(PORT R (::0.00) (::0.00))<br />
(IOPATH CLK Q (::0.40) (::0.47))<br />
(IOPATH R Q (::0.00) (::0.55))<br />
(IOPATH CLK QB (::0.45) (::0.36))<br />
(IOPATH R QB (::0.53) (::0.00))))<br />
(TIMINGCHECK<br />
(SETUP D (posedge ( posedge CLK) (0.47))<br />
(HOLD D (posedge ( posedge CLK) (-0.06)))) ( 0.06))))
<strong>Design</strong> for test & test generation<br />
�� Consider test during the design phase<br />
– Test design more difficult after design frozen<br />
�� Basic steps:<br />
– <strong>Design</strong> for test (DFT) – insert test points, scan<br />
chains, etc. to improve testability<br />
– Insert built-in built in self-test self test (BIST) circuits<br />
– Generate test patterns (ATPG)<br />
– Determine fault coverage (Fault Simulation)
DFT & test design flow<br />
Memory<br />
& Logic<br />
BIST Boundary<br />
Scan<br />
Internal<br />
Scan <strong>Design</strong><br />
ATPG
DFTadvisor/FastScan <strong>Design</strong> <strong>Flow</strong><br />
DFT/ATPG<br />
Library:<br />
adk.atpg<br />
count4.vhd<br />
count4_0.vhd<br />
count4.v<br />
count4_scan.v<br />
Source: FlexTest Manual
VHDL/Verilog<br />
Netlist With<br />
Scan Elements<br />
<strong>ASIC</strong> DFT <strong>Flow</strong><br />
DFT Advisor<br />
Synthesized VHDL/Verilog Netlist<br />
Fastscan/<br />
Flextest<br />
Insert Internal<br />
Scan Circuitry<br />
Generate/Verify<br />
Test Vectors<br />
Test Pattern File<br />
ATPG Library<br />
adk.atpg
Example DFTadvisor session<br />
�� Invoke:<br />
– dftadvisor –verilog verilog count4.v –lib lib $ADK/technology/adk.atpg<br />
$ADK/technology/ adk.atpg<br />
�� Implement scan with defaults:<br />
(full scan, mux-DFF mux DFF scan elements)<br />
– set system mode setup<br />
– analyze control signals –auto auto<br />
– set system mode dft<br />
– run<br />
– insert test logic<br />
– write netlist count4_scan.v –verilog verilog<br />
– write atpg setup count4_scan<br />
(creates (creates count4_scan.dofile for for ATPG ATPG in in Fastscan))<br />
Fastscan
count4 – without scan design
count4 – scan inserted by DFTadvisor
�� Invoke:<br />
ATPG with FastScan<br />
(full-scan (full scan circuit)<br />
– fastscan –verilog verilog count4.v –lib lib $ADK/technology/adk.atpg<br />
$ADK/technology/ adk.atpg<br />
�� Generate test pattern file:<br />
– dofile count4_scan.dofile (defines scan path & procedure)<br />
– set system mode atpg<br />
– create patterns –auto auto (generate test patterns)<br />
– save patterns<br />
Note: “count4_scan.dofile” created by DFTadvisor
Test file: scan chain definition and<br />
load/unload procedures<br />
scan_group "grp1" =<br />
scan_chain "chain1" =<br />
scan_in = "/scan_in1";<br />
scan_out = "/output[3]";<br />
length = 4;<br />
end;<br />
procedure shift "grp1_load_shift" =<br />
force_sci "chain1" 0;<br />
force "/clock" 1 20;<br />
force "/clock" 0 30;<br />
period 40;<br />
end;<br />
procedure shift "grp1_unload_shift" =<br />
measure_sco "chain1" 10;<br />
force "/clock" 1 20;<br />
force "/clock" 0 30;<br />
period 40;<br />
end;<br />
procedure load "grp1_load" =<br />
force "/clear" 0 0;<br />
force "/clock" 0 0;<br />
force "/scan_en "/ scan_en" " 1 0;<br />
apply "grp1_load_shift" 4 40;<br />
end;<br />
procedure unload "grp1_unload" =<br />
force "/clear" 0 0;<br />
force "/clock" 0 0;<br />
force "/scan_en "/ scan_en" " 1 0;<br />
apply "grp1_unload_shift" 4 40;<br />
end;<br />
end;
Generated scan-based scan based test<br />
// send a pattern through the scan chain<br />
CHAIN_TEST =<br />
pattern = 0;<br />
apply "grp1_load" 0 = (use grp1_load procedure)<br />
chain "chain1" = "0011"; (pattern to scan in)<br />
end;<br />
apply "grp1_unload" 1 = (use grp1_unload procedure)<br />
chain "chain1" = "1100"; (pattern scanned out)<br />
end;<br />
end;<br />
// one of 14 patterns for the counter circuit<br />
pattern = 0; (pattern #)<br />
apply "grp1_load" 0 = (load scan chain)<br />
chain "chain1" = "1000"; (scan-in (scan in pattern)<br />
end;<br />
force "PI" "00110" 1; (PI pattern)<br />
measure "PO" "0010" 2; (expected POs)<br />
pulse "/clock" 3; (normal op. cycle)<br />
apply "grp1_unload" 4 = (read scan chain)<br />
chain "chain1" = "0110"; (expected pattern)<br />
end;
<strong>ASIC</strong> Physical <strong>Design</strong> (Standard Cell)<br />
Generate<br />
Mask Data<br />
Std. Cell<br />
Layouts<br />
Libraries<br />
Process Data<br />
<strong>Design</strong> Rules<br />
IC Mask Data<br />
(can also do full custom layout)<br />
Component-Level Netlist (EDDM format)<br />
<strong>Design</strong> Rule<br />
Check<br />
Floorplan<br />
Chip/Block<br />
Place & Route<br />
Std. Cells<br />
ICblocks<br />
Backannotate<br />
Schematic<br />
Mach TA/Eldo Simulation Model<br />
<strong>Mentor</strong> <strong>Graphics</strong><br />
“IC Station”<br />
(adk_ic)<br />
Layout vs.<br />
Schematic<br />
Check<br />
Calibre Calibre Calibre
Cell-Based Cell Based IC
Cell-Based Cell Based Block
Basic standard<br />
Cell layout<br />
Source: Weste “CMOS VLSI <strong>Design</strong>”
Preparation for Layout<br />
1. Use <strong>Design</strong> Architect-IC Architect IC to convert Verilog netlist to<br />
<strong>Mentor</strong> <strong>Graphics</strong> EDDM netlist format<br />
– Invoke <strong>Design</strong> Architect-IC<br />
Architect IC ((adk_daic adk_daic))<br />
– On menu bar, select File File > > Import Import Verilog Verilog<br />
�� Netlist file: count4.v count4.v (the (the Verilog Verilog netlist)) netlist<br />
�� Output directory: count4 count4 (for the EDDM netlist) netlist<br />
�� Mapping file $ADK/technology/adk_map.vmp<br />
$ADK/technology/ adk_map.vmp<br />
2. Open the generated schematic for viewing<br />
– Click Schematic Schematic in DA-IC DA IC palette<br />
– Select schematic in directory named above (see next slide)<br />
– Click Update Update LVS LVS in the schematic palette to create a netlist to<br />
be used later by “Calibre Calibre”<br />
3. Create design viewpoints for ICstation tools<br />
– adk_dve adk_dve count4 count4 ––t t tsmc035 tsmc035 (V.P V.P’s: : layout, lvs, lvs,<br />
sdl, sdl,<br />
tsmc035)<br />
�� Can also create gate/transistor schematics directly in<br />
DA-IC DA IC using components from the ADK library
DA-IC DA IC generated schematic
Eldo simulation from DA-IC DA IC<br />
�� Run simulations from within DA-IC DA IC<br />
– Eldo, Eldo,<br />
ADVance ADVance MS, MS,<br />
Mach Mach TA TA<br />
�� DA-IC DA IC invokes a “netlister netlister” to create a<br />
circuit model from the schematic<br />
– SPICE model for Eldo Eldo & Mach Mach TA TA<br />
�� Eldo analyses, forces, probes, etc. same<br />
as SPICE<br />
�� View results in EZwave EZwave or Xelga<br />
Xelga
Eldo input and output files<br />
-Netlist<br />
-Simulation cmds<br />
-Stimulus
SPICE “circuit” file generated by DA-IC<br />
Force values (created interactively)<br />
From ADK<br />
library<br />
SPICE netlist for modulo7 counter
Eldo simulation of modulo7 counter<br />
(transient analysis)
Create a std-cell std cell based logic block<br />
in IC Station<br />
�� Invoke: adk_ic adk_ic<br />
�� In IC Station palette, select: Create Create Cell Cell<br />
– Cell name: count4 count4<br />
– Attach library: $ADK/technology/ic/process/tsmc035<br />
– Process: $ADK/technology/ic/process/tsmc035<br />
– Rules file: $ADK/technology/ic/process/tsmc035.rules<br />
– Angle mode: 45 45<br />
– Cell type: block block<br />
– Select With With connectivity<br />
connectivity<br />
– EDDM schematic viewpoint: count4/layout<br />
count4/layout<br />
– Logic loading options: flat<br />
flat
Create Cell dialog box
Auto-”floorplan<br />
Auto floorplan” the block<br />
place place & & route route > > autofp<br />
autofp
Auto-place Auto place the std cells<br />
Autoplc Autoplc > > StdCel<br />
StdCel
Auto-place Auto place “ports<br />
ports” ((Autoplc Autoplc > > Ports) Ports)<br />
Signal connections on cell boundaries
AutoRoute all nets<br />
(hand-route (hand route any unrouted “overflows overflows”)<br />
Then: Add > Port Text to copy port names from schematic – for Calibre
Layout design rule check (DRC)<br />
�� Technology-specific Technology specific design rules specify<br />
minimum sizes, spacing, etc. of features<br />
to ensure reliable fabrication<br />
– <strong>Design</strong> rules file specified at startup<br />
Ex. tsmc035.rules<br />
tsmc035.rules<br />
�� From main palette, select ICrules<br />
– Click Check Check and then OK OK in prompt box<br />
(can optionally select a specific area to check)<br />
– Rules checked in numeric order
Common errors detected by DRC<br />
�� To fix, click on First First in palette to highlight first<br />
error<br />
– Error is highlighted in the layout<br />
– Click View View to zoom in to the error (see next)<br />
– Example: DRC9_2: Metal2 spacing = 3L<br />
– Fix by drawing a rectangle of metal2 to fill in the gap<br />
between contacts that should be connected<br />
�� Click Next Next to go to next error, until all are fixed<br />
NOTE: There can be no DRC errors if MOSIS is to<br />
fabricate the chip – they will run their own DRC.
Error: DRC9_2 metal2 spacing = 3L<br />
Draw<br />
rectangle<br />
of metal2<br />
to fill gap
Layout vs schematic check<br />
Calibre Interactive LVS<br />
�� From ICstation menu: Calibre Calibre > > Run Run LVS LVS<br />
– In popup, Calibre location: $MGC_HOME/../Calibre<br />
$MGC_HOME/../ Calibre<br />
– Rules: $ADK/technology/ic/process/tsmc035.calibre.rules<br />
– Input: count4.src.net count4.src.net (previously created in DA-IC) DA IC)<br />
– H-cells: cells: $ADK/technology/adk.hcell<br />
$ADK/technology/ adk.hcell (hierarchical cells)<br />
– Extracted file: count4.lay.net<br />
count4.lay.net<br />
�� Compares extracted transistor-level<br />
transistor level netlist vs.<br />
netlist saved in DA-IC DA IC
Post-layout Post layout parameter extraction<br />
Calibre Interactive PEX<br />
�� Extract Spice netlist, netlist,<br />
including parasitic RC<br />
– Simulate in Eldo or MachTA<br />
�� ICstation menu: Calibre>Run Calibre>Run<br />
PEX PEX<br />
– Options Options similar similar to to Calibre Calibre LVS LVS<br />
– Extraction Extraction options: options:<br />
�� lumped lumped C C + + coupling coupling cap’’ss cap<br />
�� distributed distributed RC RC<br />
�� distributed distributed RC RC + + coupling coupling cap’’ss cap<br />
– Output file: count4.pex.netlist
Post-layout Post layout simulation with MachTA<br />
�� MachTA is an accelerated Spice simulator<br />
– Digital & mixed-signal mixed signal circuits<br />
– Analyze timing effects pre- pre and post-layout post layout<br />
�� SPICE netlists with parasitic R/C<br />
– Execute test vector file to verify functionality<br />
�� Algorithms support large designs<br />
– Partition design, simulate only partitions with changes<br />
– Combine time-driven time driven & event-driven event driven operation<br />
– Solves linearized models using a proprietary highperformance,<br />
graph-theory based, matrix solution<br />
algorithm
Mach TA flow diagram<br />
$ADK/technology/mta/tsmc035<br />
SPICE<br />
netlist
Post-layout Post layout simulation with Mach TA<br />
(netlist netlist extracted by Calibre PEX)<br />
�� Prepare netlist<br />
netlist (remove subcircuits for Mach TA)<br />
– Extracted netlist = count4.pex.netlist<br />
– Command: $ADK/bin/mta_prep<br />
$ADK/bin/ mta_prep count4 count4<br />
– Creates SPICE file: count4.sp count4.sp<br />
�� Invoke Mach TA:<br />
ana ana - command file to initialize Anacad SW<br />
mta mta ––ezw ezw ––t t $ADK/technology/mta/tsmc035 count4.sp count4.sp<br />
� Mach PA (mpa) does current & power analysis
Sample Mach TA “dofile dofile”<br />
(transient analysis)<br />
Signals to observe in EZwave<br />
plot v(clk) v(clk)<br />
v(q[2]) v(q[1]) v(q[0])<br />
measure rising TRIG v(clk) v(clk)<br />
VAL=2.5v RISE=1 TARG v(q[0]) VAL=2.5v<br />
l load<br />
l reset<br />
h count<br />
Measure time from rising edge of clk (TRIGger)<br />
l clk<br />
to 1st rising edge of q[0] (TARGet) - voltages<br />
run 5 ns<br />
h reset<br />
h clk<br />
Drive signals low/high (Lsim format)<br />
run 5 ns<br />
l clk<br />
run 5 ns<br />
Simulate for 5 ns<br />
h clk<br />
run 5 ns<br />
Command to execute: dofile file.do
Double-click<br />
signal name<br />
to display.<br />
EZwave waveform viewer<br />
(results for previous dofile) dofile
Alternative Mach TA “dofile dofile”<br />
(same result as previous example)<br />
plot v(clk) v(clk)<br />
v(q[2]) v(q[1]) v(q[0])<br />
measure rising TRIG v(clk) v(clk)<br />
VAL=2.5v RISE=1 TARG v(q[0])<br />
VAL=2.5v<br />
vpulse Vclk clk 0 pulse(0 3.3 10n .05n .05n 10n 20n)<br />
v-levels delay rise fall width period<br />
l load<br />
l reset<br />
Nodes to which<br />
h count<br />
run 5 ns<br />
source connected<br />
Periodic pulses<br />
h reset<br />
run 200 ns<br />
Voltage source name
Mach TA – test vector file<br />
�� Verify design functionality/behavior<br />
– apply test vectors<br />
– capture outputs<br />
– compare outputs to expected result<br />
– vectors/outputs from behavioral simulation<br />
�� Command to execute a test vector file:<br />
run run ––tvend tvend tvfile.tv tvfile.tv<br />
test vector file (next slide)
Test vector file format<br />
# Test vector file for modulo7 counter<br />
CODEFILE<br />
UNITS ps<br />
RISE_TIME 50<br />
FALL_TIME 50<br />
signal order within vectors<br />
Header<br />
INPUTS clk,reset,load,count,i[2],i[1],i[0];<br />
OUTPUTS q[2] (to=max),q[1] (to=max),q[0] (to=max);<br />
CODING(ROM)<br />
RADIX 3;<br />
Vector format<br />
@0 X;<br />
@2000 0;<br />
@7000 0;<br />
@10000 5;<br />
Sample 5 fs before next vector<br />
@20000 5;<br />
@30000 6;<br />
@40000 6;<br />
@50000 0;<br />
@60000 0;<br />
….. ..<br />
END<br />
Vectors: @time expected_output<br />
Test vectors derived from behavioral simulation results
Behavioral simulation listing Corresponding Mach TA test vector file
Alternate test vector file<br />
(clock generated separately by voltage source)<br />
vpulse vclk clk 0<br />
pulse(0 3.3 10n .5n .5n 10n 20n)<br />
Can mix other simulation<br />
commands with test vector<br />
application.
Xilinx “ISE”<br />
Altera “Max Plus 2”<br />
Physical <strong>Design</strong> - FPGA<br />
User-Specified<br />
Constraints<br />
Component-Level Netlist<br />
Generate<br />
Programming<br />
Data<br />
Configuration File<br />
Map to FPGA<br />
LUTs, FFs, IOBs<br />
Place & Route<br />
Generate<br />
Timing Model<br />
Simulation Model<br />
FPGA/PLD<br />
Technology<br />
Files
Xilinx/Altera<br />
Xilinx/ Altera FPGA/CPLD <strong>Design</strong><br />
�� Technology files & libraries for front-end front end design with<br />
<strong>Mentor</strong> <strong>Graphics</strong> tools<br />
– Schematic symbols for <strong>Design</strong> <strong>Design</strong> Architect Architect<br />
– Simulation models for Quicksim Quicksim II, II, Quicksim Quicksim Pro Pro<br />
– Synthesis library for Leonardo Leonardo<br />
�� Vendor tools for back-end back end design<br />
(map, place, route, configure, timing)<br />
– Xilinx Integrated Integrated Software Software Environment Environment (ISE)<br />
– Altera Quartus Quartus II II & & Max+Plus2<br />
Max+Plus2