Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuidevChapter 5: Using NC-Verilog with Synopsys ModelsNC-Verilog Utilities Reference Pages$lm_log_test_vectors Command ReferenceThe $lm_log_test_vectors command enables test vector logging for a specified instance,and specifies a file name for the test vector log.Syntax$lm_log_test_vectors (“instance_path”, on_off, “filename”)Argumentsinstance_pathon_offfilenameSpecifies the pathname of the model instance for which testvector logging is to be enabled or disabled.Indicates whether test vector logging is to be enabled ordisabled. Allowed values are 1 to enable logging, or 0 (thedefault) to disable logging.Specifies the file name to be used for the test vector log.DescriptionEnables test vector logging for a specified instance and specifies a filename for the testvector log. By default, test vector logging is not performed. When test vector logging ison, the pin value information created during the simulation for the specified deviceinstance is written in test vector file format to filename.For detailed information about test vector logging, refer to the ModelSource User’sManual or the LM-family Modeler Manual.ExampleThe following example enables test vector logging for the instance “U1”, and saves thetest vector log in the file “U1.log”.$lm_log_test_vectors (“Tbench.U1”, 1, “U1.log”);October 6, 2003 Synopsys, Inc. 99