Simulator Configuration Guide for Synopsys Models

Chapter 5: Using NC-Verilog with Synopsys ModelsSimulator Configuration GuideNC-Verilog Utilities SummaryThe following hardware model utilities are supported in NC-Verilog:$lm_log_test_vectors (“instance_path”, on_off, “filename”)The $lm_log_test_vectors command enables test vector logging for a specified instance,and specifies a file name for the test vector log.$lm_loop_instance (“instance_path”)The $lm_loop_instance command enables the loop mode for a specified model instance.For a detailed syntax description, refer to “$lm_loop_instance Command Reference” onpage 100.$lm_timing_information (“instance_path”, “timing_option”)The $lm_timing_information command lets you override the hardware modeler’sdefault handling of timing information for a specified model instance. For a detailedsyntax description, refer to “$lm_timing_information Command Reference” onpage 101.$lm_timing_measurements (“instance_path”, on_off, “filename”)The $lm_timing_measurements command enables timing measurements for a specifiedmodel instance. It is not supported for ModelSource 3200 and 3400. For a detailedsyntax description, refer to “$lm_timing_measurements Command Reference” onpage 102.$lm_unknowns (“option=value” [,”option=value”,...] [, “device_or_pin”])The $lm_unknowns command lets you override the hardware modeler’s defaulthandling of unknown values for specified instances or pins, or for all hardware modelinstances in the simulation. For a detailed syntax description, refer to “$lm_unknownsCommand Reference” on page 103.98 Synopsys, Inc. October 6, 2003