Simulator Configuration Guide for Synopsys Models

Chapter 5: Using NC-Verilog with Synopsys ModelsSimulator Configuration GuideThis step produces a bused Verilog wrapper file named model_mx_bw.v.5. Instantiate the model_mx_bw model in your design, defining the ports and SWIFTparameters as needed. The wrapper files include default values for the requiredSWIFT parameters. You can override these values as needed in your testbench. Fordetails on the required SWIFT parameters and DWMM instantiation examples, see“DesignWare Memory Model SWIFT Parameters” on page 29.HintFor model-specific instantiation examples, see the individual modeldatasheets. You can cut-and-paste the model instantiation right out of themodel datasheet and drop it into your testbench. Be sure to map signalnames in your design to the model’s ports. You can access the correct modeldatasheet for the version of the model that you are using with the sl_browsertool ($LMC_HOME/bin/sl_browser).6. There is no need to build a Verilog executable. You can use the one from$CDS_INST_DIR/tools/bin by adding it to your path statement.7. Invoke NC-Verilog to compile and simulate your design, as shown in the followingexample:% ncverilog \model_mx.v \model_mx_bw.v \testbench.v \+incdir+$LMC_HOME/sim/pli/src \+loadpli1=swiftpli:swift_boot \+ncaccess+r+w8. If you are using the ncvlog, ncelab, and ncsim flow, create cds.lib and hdl.var filesin the directory where you will be executing these commands.Contents of cds.lib file:SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/cds.libDEFINE worklib ./worklibContents of hdl.var file:SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/hdl.var96 Synopsys, Inc. October 6, 2003