Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuidevChapter 5: Using NC-Verilog with Synopsys Models9. Execute the ncvlog, ncelab, and ncsim commands as follows:% ncvlog -w worklib testbench.v \./workdir/examples/verilog/model.v \./workdir/examples/verilog/model_fx_vxl.v \-incdir $LMC_HOME/sim/pli/src \-incdir ./workdir/src/verilog% ncelab -messages worklib.testbench \-loadpli1 swiftpli:swift_boot \-access +rw% ncsim worklib.testbenchFor information on LMTV commands that you can use with FlexModels on NC-Verilog,refer to “LMTV Commands” on page 271.Using DesignWare Memory Models withNC-VerilogDesignWare Memory Models (DWMM) are SWIFT-compatible binary simulationmodels, and have an _mx extension (for example, model_mx). DWMM models workwith NC-Verilog using a PLI application called LMTV that is delivered in the form of aswiftpli shared library in $LMC_HOME/lib/platform.lib.For information on static linking LMTV, see “Static Linking with LMTV” on page 268.To use the prebuilt swiftpli, follow this procedure:1. Make sure NC-Verilog is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 89.2. If you are using DWMM testbench commands in your design, add the followingline to your Verilog testbench:`include "mempro_pkg.v"For information on using the DWMM testbench commands, refer to the DesignWareMemory Model User’s Manual.3. Generate a bit-blasted Verilog wrapper file for the model, as shown in the followingexample:% $LMC_HOME/bin/vsg -bit -z model_mxThis step produces a bit-blasted Verilog wrapper file named model_mx.v.4. Generate a bused Verilog wrapper file for the model, as shown in the followingexample:% $LMC_HOME/bin/vsg -bit2bus verilog model_mxOctober 6, 2003 Synopsys, Inc. 95