Simulator Configuration Guide for Synopsys Models

Chapter 5: Using NC-Verilog with Synopsys ModelsSimulator Configuration Guide5. Instantiate FlexModels in your design, defining the ports and defparams as required(refer to the example testbench supplied with the model). You use the supplied buslevelwrapper (model.v) in the top-level of your design to instantiate the suppliedbit-blasted wrapper (model_fx_vxl.v).Example using bus-level wrapper (model.v) without timing:model U1 ( model ports )defparamU1.FlexModelId = “TMS_INST1”;Example using bus-level wrapper (model.v) with timing:model U1 ( model ports )defparamU1.FlexTimingMode = `FLEX_TIMING_MODE_ON,U1.TimingVersion = “timingversion“,U1.DelayRange = “range“,U1.FlexModelId = “TMS_INST1”;6. There is no need to build a Verilog executable. You can use the one from$CDS_INST_DIR/tools/bin by adding it to your path statement.7. Invoke the NC-Verilog simulator to compile and simulate your design as shown inthe following examples:UNIX% ncverilog testbench +loadpli1=swiftpli:swift_boot \./workdir/examples/verilog/model.v \./workdir/examples/verilog/model_fx_vxl.v \+incdir+$LMC_HOME/sim/pli/src \+incdir+workdir/src/verilog \\+ncaccess+r+w8. If you are using the ncvlog, ncelab, and ncsim flow, create cds.lib and hdl.var filesin the directory where you will be executing these commands.Contents of cds.lib file:SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/cds.libDEFINE worklib ./worklibContents of hdl.var file:SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/hdl.var94 Synopsys, Inc. October 6, 2003