Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuidevChapter 5: Using NC-Verilog with Synopsys Models5Using NC-Verilog withSynopsys ModelsOverviewThis chapter explains how to use SmartModels, FlexModels, DesignWare MemoryModels, and hardware models with NC-Verilog. The procedures are organized into thefollowing major sections:● “Setting Environment Variables” on page 89● “Using SmartModels with NC-Verilog” on page 91● “Using FlexModels with NC-Verilog” on page 92● “Using DesignWare Memory Models with NC-Verilog” on page 95● “Using Hardware Models with NC-Verilog” on page 97Setting Environment VariablesFirst, set the basic environment variables. If you are not using one of the model types,skip that step. In some cases, the procedures in this chapter include steps for settingadditional environment variables.1. Set the LMC_HOME environment variable to point to the location of yourSmartModel, FlexModel, or DesignWare Memory Model installation tree, asfollows:% setenv LMC_HOME path_to_models_installationOctober 6, 2003 Synopsys, Inc. 89