Simulator Configuration Guide for Synopsys Models

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Chapter 4: Using ModelSim VHDL with Synopsys ModelsSimulator Configuration GuideModelSim VHDL UtilitiesThe following hardware modeler simulator commands are supported in ModelSimVHDL:lm_vectors on | off instance_name filenameThe lm_vectors utility turns on vector logging for the hardware model instance. Thevectors record stimulus to the input and I/O pins and responses from the output and I/Opins during simulation.lm_measure_timing on | off instance_name filenameThe lm_measure_timing utility causes the modeler to measure timing between an inputtransition and resulting output transition on the hardware model. Note that this is onlysupported on LM-family systems.lm_timing_checks on | off instance_nameThe lm_timing_checks utility allows you to enable or disable timing checks such assetups and holds.lm_loop_patterns on | off instance_nameThe lm_loop_patterns utility causes the hardware modeler to continually replay thepattern history of a specified device instance.lm_unknowns on | off instance_nameThe lm_unknowns utility turns off unknown propagation. This “on_unknown” featureis also in the .OPT file for hardware models. It modifies the system's default handling ofdevice input and I/O pins that are set to unknown by the simulator. This utility does notturn on unknown propagation unless it is also turned on in the .OPT file, but it canoverride the setting in the .OPT file to turn this feature off when it is set to on in the.OPT file.88 Synopsys, Inc. October 6, 2003
Simulator Configuration GuidevChapter 5: Using NC-Verilog with Synopsys Models5Using NC-Verilog withSynopsys ModelsOverviewThis chapter explains how to use SmartModels, FlexModels, DesignWare MemoryModels, and hardware models with NC-Verilog. The procedures are organized into thefollowing major sections:● “Setting Environment Variables” on page 89● “Using SmartModels with NC-Verilog” on page 91● “Using FlexModels with NC-Verilog” on page 92● “Using DesignWare Memory Models with NC-Verilog” on page 95● “Using Hardware Models with NC-Verilog” on page 97Setting Environment VariablesFirst, set the basic environment variables. If you are not using one of the model types,skip that step. In some cases, the procedures in this chapter include steps for settingadditional environment variables.1. Set the LMC_HOME environment variable to point to the location of yourSmartModel, FlexModel, or DesignWare Memory Model installation tree, asfollows:% setenv LMC_HOME path_to_models_installationOctober 6, 2003 Synopsys, Inc. 89
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PrefaceSimulator Configuration Guid
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Chapter 1: Using Synopsys Models wi
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Chapter 9: Using VERA with Synopsys
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Chapter 10: Using SystemC with Syno
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Appendix A: Using LMTV with Synopsy
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Appendix B: Using Custom Memory Mod
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Simulator Configuration Guide for Synopsys Models

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