Simulator Configuration Guide for Synopsys Models

Chapter 4: Using ModelSim VHDL with Synopsys ModelsSimulator Configuration GuideAttentionTo use the bused model wrapper, you must add appropriate componentdeclarations to your testbench or edit a component file already included inyour testbench for multiple SWIFT models, specifying ports and generics asrequired.12. Instantiate the model in your design using either the bit-blasted wrapper(model_mx) or the bused wrapper (model_mx_bw). Define the ports and SWIFTparameters as needed. The wrapper files include default values for the requiredSWIFT parameters. You can override these values as needed in your testbench. Fordetails on the required SWIFT parameters and DWMM instantiation examples, see“DesignWare Memory Model SWIFT Parameters” on page 29.HintFor model-specific instantiation examples, see the individual modeldatasheets. You can copy the model instantiation directly from the modeldatasheet and paste it into your testbench. Be sure to map signal names in yourdesign to the model’s ports. You can access the model datasheet for yourmodel version using the sl_browser tool ($LMC_HOME/bin/sl_browser).13. Compile your testbench (example assumes you are in its directory):% vcom -93 testbench.vhd14. Invoke MTI VHDL and simulate your design:% vsim testbench_configurationFor information on how to use ModelSim VHDL, refer to the ModelSim User’sManual.Using Hardware Models with ModelSimVHDLTo use hardware models with ModelSim VHDL, follow this procedure:1. Make sure ModelSim VHDL is set up properly, and all required environmentvariables are set, as explained in “Setting Environment Variables” on page 73.2. Add the hardware model install tree to your path variable, as shown in the followingexample:% set path=(/install/sms/bin/your_platform/ $path)84 Synopsys, Inc. October 6, 2003