Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuideChapter 4: Using ModelSim VHDL with Synopsys Models7. Compile the FlexModel VHDL files into logical library slm_lib as follows:% mti_path/bin/vcom -work slm_lib $LMC_HOME/sim/mti/src/slm_hdlc.vhd% mti_path/bin/vcom -work slm_lib $LMC_HOME/sim/mti/src/flexmodel_pkg.vhd% mti_path/bin/vcom -work slm_lib workdir/src/vhdl/model_user_pkg.vhd% mti_path/bin/vcom -work slm_lib workdir/src/vhdl/model_pkg.vhd% mti_path/bin/vcom -work slm_lib workdir/examples/vhdl/model_fx_comp.vhd% mti_path/bin/vcom -work slm_lib workdir/examples/vhdl/model_fx_mti.vhd% mti_path/bin/vcom -work slm_lib workdir/examples/vhdl/model.vhd8. Add LIBRARY and USE statements to your testbench:library slm_lib;use slm_lib.flexmodel_pkg.all;use slm_lib.model_pkg.all;use slm_lib.model_user_pkg.all;For example, you would use the following statement for the tms320c6201_fxmodel:use slm_lib.tms320c6201_pkg.all;use slm_lib.tms320c6201_user_pkg.all;9. Instantiate FlexModels in your design, defining the ports and generics as required(refer to the example testbench supplied with the model). You use the suppliedbus-level wrapper (model.vhd) in the top-level of your design to instantiate thesupplied bit-blasted wrapper (model_fx_mti.vhd for UNIX).Example using bus-level wrapper (model.vhd) without timing:U1: modelgeneric map (FlexModelId => “TMS_INST1”)port map ( model ports );Example using bus-level wrapper (model.vhd) with timing:U1: modelgeneric map (FlexModelId => “TMS_INST1”,FlexTimingMode => FLEX_TIMING_MODE_ON,TimingVersion => “timingversion”,DelayRange => “range”)port map ( model ports );10. Compile the testbench as shown in the following example:% vcom testbench11. Invoke the ModelSim VHDL simulator as shown in the following example:% vsim designOctober 6, 2003 Synopsys, Inc. 81