Simulator Configuration Guide for Synopsys Models

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FiguresSimulator Configuration GuideFiguresFigure 1: run_flex_examples_in_vcs.pl Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Figure 2: Sample Pin and Bus Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Figure 3: Visible Symbol Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129Figure 4: National Semiconductor DP8429 DRAM Controller . . . . . . . . . . . . . . . 148Figure 5: Bus and Pin Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150Figure 6: DWMM Visible Symbol Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153Figure 7: Sample Component Interface for a Hardware Model . . . . . . . . . . . . . . . 168Figure 8: Hardware Model Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170Figure 9: VERA Model Class Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224Figure 10: DesignWare Memory Model with VERA Design Flow . . . . . . . . . . . . . 2298 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideTablesTablesTable 1: Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Table 2: SmartModel SWIFT Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Table 3: FlexModel SWIFT Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Table 4: FlexModel C-only Command Mode Files . . . . . . . . . . . . . . . . . . . . . . . . . 27Table 5: DesignWare Memory Model SWIFT Parameters . . . . . . . . . . . . . . . . . . . . 29Table 6: VCS SmartModel Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Table 7: FlexModel VCS Verilog Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Table 8: VCS With One FlexModel On 32-bit Solaris Model Explanation . . . . . . . 49Table 9: FlexModel ModelSim Verilog File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Table 10: FlexModel MTI VHDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Table 11: FlexModel NC-Verilog Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Table 12: FlexModel NC-VHDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Table 13: Symbol Properties used by SWIFT Models . . . . . . . . . . . . . . . . . . . . . . . 129Table 14: Symbol Properties Required for Simulation . . . . . . . . . . . . . . . . . . . . . . . 130Table 15: Optional Symbol Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131Table 16: Signal State Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135Table 17: QuickSim II Command Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137Table 18: Elements in a TIBPAL22V10 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143Table 19: Symbol Properties for DesignWare Memory Model Parameters . . . . . . . 153Table 20: Symbol Properties Required for DesignWare Memory Model Simulation 155Table 21: Optional DWMM Symbol Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156Table 22: DWMM Signal State Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159Table 23: Common Unsupported QuickSim II Commands . . . . . . . . . . . . . . . . . . . 160Table 24: Mentor Graphics Vendor CPU Operating System Suffixes . . . . . . . . . . . 165Table 25: Sample Component Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171Table 26: Shell Software to Technology File Conversion . . . . . . . . . . . . . . . . . . . . . 174Table 27: Signal Instance Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177Table 28: FlexModel Scirocco VHDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196Table 29: FlexModel Files Used with the VERA UDF Interface . . . . . . . . . . . . . . . 208Table 30: Link Line Object Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209Table 31: VERA Header Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210Table 32: FlexModel VERA Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213Table 33: Key DesignWare Memory Model VERA Files . . . . . . . . . . . . . . . . . . . . 225Table 34: VERA List File Path Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243Table 35: Valid Simultators for Using DWMM Models with VERA . . . . . . . . . . . . 244Table 36: Valid Platforms for Using DWMM Models with VERA . . . . . . . . . . . . . 244October 6, 2003 Synopsys, Inc. 9
Page 1: Simulator ConfigurationGuide for Sy
Page 4 and 5: ContentsSimulator Configuration Gui
Page 6 and 7: ContentsSimulator Configuration Gui
Page 10 and 11: TablesSimulator Configuration Guide
Page 12 and 13: PrefaceSimulator Configuration Guid
Page 18 and 19: Chapter 1: Using Synopsys Models wi
Page 40 and 41: Chapter 2: Using VCS with Synopsys
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Chapter 2: Using VCS with Synopsys
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Chapter 3: Using ModelSim Verilog w
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Chapter 4: Using ModelSim VHDL with
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Chapter 5: Using NC-Verilog with Sy
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Chapter 6: Using NC-VHDL with Synop
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Chapter 7: Using QuickSim II with S
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Chapter 8: Using Scirocco with Syno
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Chapter 9: Using VERA with Synopsys
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Chapter 10: Using SystemC with Syno
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Appendix A: Using LMTV with Synopsy
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Appendix B: Using Custom Memory Mod
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IndexSimulator Configuration Guide$
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IndexSimulator Configuration GuideS
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Simulator Configuration Guide for Synopsys Models

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