Simulator Configuration Guide for Synopsys Models

Chapter 4: Using ModelSim VHDL with Synopsys ModelsSimulator Configuration Guide6. Instantiate the SmartModel component in your testbench by specifying the requiredSWIFT parameters in the generic map. Here is an example instantiation for theTTL373 model, with the library and use statements, the instance (U1), and theTimingVersion and DelayRange options specified in the generic map for theTTL373 SmartModel Library component.Use the SmartModel Library (slm_lib) just as you would use any other VHDLresource library. Here is an example:library IEEE;use IEEE.STD_LOGIC_1164.ALL;library SLM_LIB;use SLM_LIB.COMPONENTS.ALL;entity TestBench isend TestBench;architecture ArchTestBench of TestBench issignal A, B, C: STD_LOGIC;U1 : TTL373 generic map (TimingVersion => "SN74LS373",DelayRange => "Typ")port map (A => D1, B => D2, C => Q1);P1 : processbegin........For more information on SmartModel configuration parameters, refer to “UsingSmartModels with SWIFT Simulators” on page 18.7. Compile the top-level testbench to a work library (MYWORK) as shown in thefollowing example:% vlib MYWORK% vcom -work MYWORK top.vhd8. Invoke the simulator by running vsim, as shown in the following example:% vsim -lib MYWORK CFGTESTFor information on how to use ModelSim VHDL, refer to the “ModelSim User’sManual.” Note, the design name or configuration name does not necessarily have tobe CFGTEST.78 Synopsys, Inc. October 6, 2003