Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuideChapter 4: Using ModelSim VHDL with Synopsys ModelsD7 : in std_logic;D8 : in std_logic;OC : in std_logic;Q1 : out std_logic;Q2 : out std_logic;Q3 : out std_logic;Q4 : out std_logic;Q5 : out std_logic;Q6 : out std_logic;Q7 : out std_logic;Q8 : out std_logic );end;architecture SmartModel of ttl373 isattribute FOREIGN : STRING;attribute FOREIGN of SmartModel : architecture is "sm_init$MODEL_TECH/libsm.sl ; ttl373";beginend SmartModel;library ieee; use ieee.std_logic_1164.all; package comp iscomponent ttl373generic ( TimingVersion : STRING := "SN74LS373";DelayRange : STRING := "MAX";ModelMapVersion : STRING := "01008" );port ( C : in std_logic;D1 : in std_logic;D2 : in std_logic;D3 : in std_logic;D4 : in std_logic;D5 : in std_logic;D6 : in std_logic;D7 : in std_logic;D8 : in std_logic;OC : in std_logic;Q1 : out std_logic;Q2 : out std_logic;Q3 : out std_logic;Q4 : out std_logic;Q5 : out std_logic;Q6 : out std_logic;Q7 : out std_logic;Q8 : out std_logic );end component;end comp;5. Compile the model.vhd into a library called slm_lib, as follows:% vcom -93 -work slm_lib model.vhdOctober 6, 2003 Synopsys, Inc. 77