Simulator Configuration Guide for Synopsys Models

Chapter 4: Using ModelSim VHDL with Synopsys ModelsSimulator Configuration GuideThen uncomment the libsm and libswift lines corresponding to the platform you areusing:; ModelSim’s interface to Logic Modeling’s SmartModel SWIFT software;libsm = $MODEL_TECH/libsm.sl; libsm = $MODEL_TECH/libsm.dll; Logic Modeling’s SmartModel SWIFT software (HP 9000 Series 700); libswift = $LMC_HOME/lib/hp700.lib/libswift.sl; Logic Modeling’s SmartModel SWIFT software (IBM RISC System/6000); libswift = $LMC_HOME/lib/ibmrs.lib/swift.o; Logic Modeling’s SmartModel SWIFT software (Sun4 Solaris); libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so; Logic Modeling’s SmartModel SWIFT software (Sun4 SunOS); do setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4SunOS.lib; and run "vsim.swift".; ; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll; Logic Modeling's SmartModel SWIFT software (HP64); libswift = $LMC_HOME/lib/hp64.lib/libswift.sl; Logic Modeling's SmartModel SWIFT software (Sparc64); libswift = $LMC_HOME/lib/sparc64.lib/libswift.so4. To create the SmartModel Library VHDL wrappers or templates, run the ModelSimsm_entity script with any optional arguments. The sm_entity script takesSmartModel names as input and writes the VHDL output to STDOUT. You canredirect the output to a file. Run sm_entity as follows. For more information, referto “sm_entity Command Reference” on page 79.% sm_entity -c model > model.vhdFor example:% sm_entity -c ttl373 > ttl373.vhdgenerates the following VHDL file, which has both entity and componentdeclarations for the model. Edit the resulting VHDL file to add the portions of textthat are highlighted in the following example:library IEEE;use IEEE.std_logic_1164.all;entity ttl373 isgeneric ( TimingVersion : STRING := "SN74LS373";DelayRange : STRING := "MAX";ModelMapVersion : STRING := "01008" );port ( C : in std_logic;D1 : in std_logic;D2 : in std_logic;D3 : in std_logic;D4 : in std_logic;D5 : in std_logic;D6 : in std_logic;76 Synopsys, Inc. October 6, 2003