Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuideChapter 3: Using ModelSim Verilog with Synopsys ModelsSolaris% setenv LD_LIBRARY_PATH \hardware_model_install_path/sms/ma_verilog/lib/sun4_5.6/mav.soHP-UXAIX% setenv SHLIB_PATH \hardware_model_install_path/sms/ma_verilog/lib/pa_hp102/mav.sl% setenv LIBPATH \hardware_model_install_path/sms/ma_verilog/lib/rs6000_4.1.5/mav.so5. Generate a Verilog module definition or shell for each hardware model that youwant to use by running the Synopsys-provided lmvsg script, as shown in thefollowing example:% lmvsg destination_model.MDLFor this to work, the hardware_model_install_path/sms//ma_verilog/bin/platformdirectory must be in your PATH. .6. Use the Verilog module definitions to instantiate the hardware models in yourtestbench. The following example shows an example instantiation for the TILS299hardware model Notice the two “defparam” statements; the definitions of theTimingVersion (TILS299A.MDL) and DelayRange (MIN) parameters in theinstantiation override the default definitions in the model.v file (TILS299.MDL andMAX, respectively). In this example, TILS299A.MDL represents a custom timingversion that the designer wants to use instead of the default timing versionTILS299.MDL./ Instantiate UUT : ModelSource TILS299 hardware model : U1defparam U1.TimingVersion=”TILS299A.MDL”;defparam U1.DelayRange = “MIN”;TILS299 U1(.CLK (clkw),.CLR (clrw),.A (io1w[0]),.B (io1w[1]),.C (io1w[2]),.D (io1w[3]),.E (io1w[4]),.F (io1w[5]),.G (io1w[6]),.H (io1w[7]),.G1 (g1w),.G2 (g2w),.QA (qa1w),.QH (qh1w),.S0 (s0w),.S1 (s1w),October 6, 2003 Synopsys, Inc. 69