Simulator Configuration Guide for Synopsys Models

Chapter 3: Using ModelSim Verilog with Synopsys ModelsSimulator Configuration GuideUsing DesignWare Memory Models withModelSim VerilogDesignWare Memory Models (DWMM) are SWIFT-compatible binary simulationmodels that have an _mx extension (for example, model_mx). DWMM models workwith MTI Verilog (ModelSim) using a PLI application called LMTV that is delivered inthe form of a swiftpli_mti shared library in $LMC_HOME/lib/platform.lib.For information on static linking LMTV, see “Static Linking with LMTV” on page 268.To use the prebuilt swiftpli_mti, follow this procedure:To use DWMM models with ModelSim-Verilog, follow these steps:1. Make sure ModelSim Verilog is set up properly and all required environmentvariables are set, as explained in “Setting Environment Variables” on page 59.2. Map your work library as shown in this example:% vlib work% vmap work workThis produces a modelsim.ini file.3. Edit the modelsim.ini file to uncomment the Resolution statement, and set theresolution value to 100ps, as shown in the following example.Resolution = 100psNoteIf you are using VHDL SmartModels in your Verilog simulation, you mustalso edit the modelsim.ini file to uncomment the libsm and libswift lines foryour platform (see “Using ModelSim VHDL with Synopsys Models” onpage 73).4. If you are using DWMM testbench commands in your design, add the followingline to your Verilog testbench:`include "mempro_pkg.v"For information on using the DWMM testbench commands, refer to the DesignWareMemory Model User’s Manual.66 Synopsys, Inc. October 6, 2003