Simulator Configuration Guide for Synopsys Models

Chapter 3: Using ModelSim Verilog with Synopsys ModelsSimulator Configuration GuideTable 9: FlexModel ModelSim Verilog FileFile Name Description Locationmodel_pkg.incVerilog task definitions for FlexModel interfacecommands. This file also references theflexmodel_pkg.inc and model_user_pkg.inc files.workdir/src/verilog/model_user_pkg.inc Clock frequency setup and user customizations. workdir/src/verilog/model_fx_mti.vmodel.vmodel_tst.vA SWIFT wrapper that you can use to instantiatethe model.A bus-level wrapper around the SWIFT model.This allows you to use vectored ports for themodel in your testbench.A testbench that instantiates the model and showshow to use basic model commands.workdir/examples/verilog/workdir/examples/verilog/workdir/examples/verilog/5. Update the clock frequency supplied in the model_user_pkg.inc file to correspondto the CLK period you want for the model. This file is located in:workdir/src/verilog/model_user_pkg.incwhere workdir is your working directory.6. Add the following line to your Verilog testbench to include FlexModel testbenchinterface commands in your design:`include "model_pkg.inc"NoteBe sure to add model_pkg.inc within the module from which you will beissuing FlexModel commands.Because the model_pkg.inc file includes references to flexmodel_pkg.inc andmodel_user_pkg.inc, you don’t need to add flexmodel_pkg.inc ormodel_user_pkg.inc to your testbench.7. Instantiate FlexModels in your design, defining the ports and defparams as required(refer to the example testbench supplied with the model). You use the supplied buslevelwrapper (model.v) in the top-level of your design to instantiate the suppliedbit-blasted wrapper (model_fx_mti.v).Example using bus-level wrapper (model.v) without timing:model U1 ( model ports )defparamU1.FlexModelId = “TMS_INST1”;64 Synopsys, Inc. October 6, 2003