Simulator Configuration Guide for Synopsys Models

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ContentsSimulator Configuration GuideUsing Hardware Models with QuickSim II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164Setting up Hardware Models in QuickSim II . . . . . . . . . . . . . . . . . . . . . . . . . 164Using Hardware Models in QuickSim II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166Model Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169Registering a Model with lm_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171Modifying a Hardware Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176Simulating with Hardware Models in QuickSim II . . . . . . . . . . . . . . . . . . . . . 177lm_model Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185tmg_to_ts Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188Chapter 8Using Scirocco with Synopsys Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191Setting Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191Running 32-bit Models on 64-bit Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . 192Using SmartModels with Scirocco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193create_smartmodel_lib Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . 194Using FlexModels with Scirocco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196Using DesignWare Memory Models with Scirocco . . . . . . . . . . . . . . . . . . . . . . . 199Using Hardware Models with Scirocco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201Scirocco Utilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202VHDL Model Generics with Scirocco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202Chapter 9Using VERA with Synopsys Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207Using VERA with FlexModels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207Using FlexModels with the VERA UDF Interface . . . . . . . . . . . . . . . . . . . . . 208Creating a VERA Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210VERA Testbench Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211Incorporating FlexModels in a VERA Testbench . . . . . . . . . . . . . . . . . . . . . . 213Using VERA with FlexModels and VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215Example Vera System Testbenches For FlexModels . . . . . . . . . . . . . . . . . . . . 218Using VERA with DesignWare Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . 223DesignWare Memory Models with VERA . . . . . . . . . . . . . . . . . . . . . . . . . . . 224Adding DesignWare Memory Model Commands to the VERA Testbench . . 230Building the VERA UDF Dynamic Library . . . . . . . . . . . . . . . . . . . . . . . . . . 235Compiling the VERA Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242Creating a VERA List File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243Building and Invoking the Simulator Executable . . . . . . . . . . . . . . . . . . . . . . 2446 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideContentsChapter 10Using SystemC with Synopsys Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261Setting Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261Using SmartModels with SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262Using DesignWare Memory Models with SystemC . . . . . . . . . . . . . . . . . . . . . . . 264Appendix AUsing LMTV with Synopsys Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267What is LMTV? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267Static Linking with LMTV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268Edited veriuser.c File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268LMTV Command-Line Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270LMTV Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271$lm_command() or $lai_command() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272$lm_dump_file() or $lai_dump_file() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273$lm_help() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274$lm_load_file() or $lai_load_file() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275$lm_monitor_enable() or $lai_enable_monitor() . . . . . . . . . . . . . . . . . . . . . . 276$lm_monitor_disable() or $lai_disable_monitor() . . . . . . . . . . . . . . . . . . . . . 276$lm_monitor_vec_map() and $lm_monitor_vec_unmap() . . . . . . . . . . . . . . . 278$lm_status() or $lai_status() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280Appendix BUsing Custom Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281Configuring Custom Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282Controlling Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283Instantiating Custom Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285Using Custom Memory Models with VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286Using Custom Memory Models with VCS and Verilog Testbenches . . . . . . . 286Using Custom Memory Models with VCS and C Testbenches . . . . . . . . . . . . 287Using Custom Memory Models with NC-Verilog . . . . . . . . . . . . . . . . . . . . . . . . 289Using Custom Memory Models with MTI Verilog . . . . . . . . . . . . . . . . . . . . . . . . 290Using Custom Memory Models with Scirocco . . . . . . . . . . . . . . . . . . . . . . . . . . . 292Using Custom Memory Models with MTI VHDL . . . . . . . . . . . . . . . . . . . . . . . . 294Using Custom Memory Models with NC-VHDL . . . . . . . . . . . . . . . . . . . . . . . . . 296Using Custom Memory Models with VERA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301October 6, 2003 Synopsys, Inc. 7
Page 1: Simulator ConfigurationGuide for Sy
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Page 8 and 9: FiguresSimulator Configuration Guid
Page 10 and 11: TablesSimulator Configuration Guide
Page 12 and 13: PrefaceSimulator Configuration Guid
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Chapter 2: Using VCS with Synopsys
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Chapter 2: Using VCS with Synopsys
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Chapter 3: Using ModelSim Verilog w
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Chapter 4: Using ModelSim VHDL with
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Chapter 10: Using SystemC with Syno
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Appendix A: Using LMTV with Synopsy
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Appendix B: Using Custom Memory Mod
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IndexSimulator Configuration GuideS
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Simulator Configuration Guide for Synopsys Models

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