Simulator Configuration Guide for Synopsys Models

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Chapter 2: Using VCS with Synopsys ModelsSimulator Configuration GuideHP-UX% setenv VCS_LMC_HM_ARCH pa_hp1026. Create a Verilog HDL template for the hardware model using the lmvc_templatescript provided by VCS, as shown in the following example:% lmvc_template model_filewhere model_file is the name of the hardware model's .MDL file.For example, if your model is the TILS299, enter:% lmvc_template TILS299.MDLThis step produces a TILS299.lmvc.v file that contains the module definition withall the calls, declarations, and assignments necessary to make the file a valid VCSmodule.NoteThe lmvc_template program looks for Shell Software files in the directoriesindicated by the LM_LIB environment variable. You can modify the port listgenerated by the lmvc_template to match the existing model instantiationsby editing the .NAM file.7. Compile your description. Make sure to include the hardware model template andsupporting PLI and library files. To interface the hardware modeler to VCS, add the-lmc-hm switch to the VCS command line, as shown in the following example:% vcs +plusarg_save -RI test.v TILS299.lmvc.v -lmc-hm -o simv \+override_model_delays +maxdelays -l vcs.log &You can optionally invoke VCS without the -lmc-hm switch by using the -P switchto point to the $VCS_LMC/lmvc.tab file and including the $VCS_LMC/lmvc.oobject file and $LM_SFI/lm_sfi.a library, as shown in the following example:% vcs +plusarg_save -RI test.v TILS299.lmvc.v -P $VCS_LMC/lmvc.tab \$VCS_LMC/lmvc.o $LM_SFI/lm_sfi.a -o simv \+override_model_delays +maxdelays -l vcs.log &where:• vcs is the compiler• test.v is the file that is part of the top level system source files• TILS299.lmvc.v is the vcs template for the HW model• lmvc.tab is the VCS file for lmvc calls for vector logging, and timingmeasurement• lmvc.o is the object code for LMC C file (lmvc.c), which contains thedefinitions for all the lmvc tasks/functions.56 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideChapter 2: Using VCS with Synopsys Models• lm_sfi.a is the simulator function interface software that links the VCSsimulator to the hardware modeler.• +override_model_delays is a switch that allows you to specify timing otherthan typical.Notethe -RI option is not required to generate the simv file. It is used to have thesimulator automatically execute after compilation.For more information on using the .tab/.c files and options with VCS, refer to the VCSUsers's Guide.Note that in the previous VCS releases, the hardware model could only be simulatedwith typical delays. The VCS 5.2 release has removed this restriction, so you can noweither use a runtime option on the command line or make the change in the DelayRangeparameter. Note that the runtime option does override any DelayRange parameterspecification. The following excerpt is from the VCS 5.2 Release Notes:“VCS 5.2 has a new runtime option, +override_model_delays that enables you touse the +mindelays, +typdelays, or +maxdelays runtime option to specify timing inSWIFT SmartModels or Synopsys hardware models and in so doing override theDelayRange parameter in the template files for these models that otherwisespecifies the timing for the model.”Example Using Runtime OptionHere is an example using the runtime option:% vcs +plusarg_save -RI test.v TILS299.lmvc.v -P $VCS_LMC/lmvc.tab \$VCS_LMC/lmvc.o $LM_SFI/lm_sfi.a +override_model_delays \+maxdelays -l vcs.log &Example Using DelayRange ParameterHere is an example using the DelayRange parameter:TILS299 hwm_1 ( .\SL (shift_left), .\CLK (clock),.\SR (shift_right), .\NCLR (clear),.\-G2 (g2), .\-G1 (g1), .\S1 (select_1), .\S0 (select_0),.\D/QD (bit_4), .\F/QF (bit_6), .\B/QB (bit_2),.\C/QC (bit_3), .\A/QA (bit_1), .\G/QG (bit_7), .\E/QE (bit_5),.\H/QH (bit_8), .\QA (high_bit), .\QH (low_bit) );`ifdef MAXdefparam hwm_1.DelayRange = "MAX" ;`endifOctober 6, 2003 Synopsys, Inc. 57
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Simulator ConfigurationGuide for Sy
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ContentsSimulator Configuration Gui
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Page 8 and 9: FiguresSimulator Configuration Guid
Page 10 and 11: TablesSimulator Configuration Guide
Page 12 and 13: PrefaceSimulator Configuration Guid
Page 18 and 19: Chapter 1: Using Synopsys Models wi
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Chapter 5: Using NC-Verilog with Sy
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Chapter 6: Using NC-VHDL with Synop
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Chapter 9: Using VERA with Synopsys
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Chapter 10: Using SystemC with Syno
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Appendix A: Using LMTV with Synopsy
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Appendix B: Using Custom Memory Mod
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IndexSimulator Configuration Guide$
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