Simulator Configuration Guide for Synopsys Models

Chapter 2: Using VCS with Synopsys ModelsSimulator Configuration GuideThis step produces a bit-blasted Verilog wrapper file named model_mx.v and abused Verilog wrapper file named model_mx_bus.v. The wrapper files both containan InstanceName parameter along with the following instructions:// Please insert instance name here...// **and uncomment this lineDo not follow these instructions. The InstanceName parameter is not needed forinstantiating DWMM models (see the next step).4. Instantiate the model_mx_bus model in your design, defining the ports and SWIFTparameters as needed. The wrapper files include default values for the requiredSWIFT parameters. You can override these values as needed in your testbench. Fordetails on the required SWIFT parameters and DWMM instantiation examples, see“DesignWare Memory Model SWIFT Parameters” on page 29.HintFor model-specific instantiation examples, see the individual modeldatasheets. You can cut-and-paste the model instantiation right out of themodel datasheet and drop it into your testbench. Be sure to map signalnames in your design to the model’s ports. You can access the correct modeldatasheet for the version of the model that you are using with the sl_browsertool ($LMC_HOME/bin/sl_browser).5. Invoke VCS to compile your design, as shown in the following example:% vcs \model_mx_bus.v \testbench.v \-lmc-swift \-P $LMC_HOME/sim/pli/src/slm_pli.tab \$LMC_HOME/lib/platform.lib/slm_pli.o \+incdir+$LMC_HOME/sim/pli/src54 Synopsys, Inc. October 6, 2003