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Simulator Configuration Guide for Synopsys Models

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<strong>Simulator</strong> <strong>Configuration</strong> <strong>Guide</strong>Chapter 2: Using VCS with <strong>Synopsys</strong> <strong>Models</strong>Example <strong>Simulator</strong> Run ScriptThe run_flex_examples_in_vcs.pl script also creates an example simulator run script inyour current working directory <strong>for</strong> the specified model. You can use this run script toinvoke VCS after running the run_flex_examples_in_vcs.pl script. The followingexample shows the contents of the “Example_<strong>Simulator</strong>_Run_Script” after running therun_flex_examples_in_vcs.pl script using the mpc860_fx model.# This is an example of VCS command line to run the supplied FlexModeltestbench.# Note: The model version was calculated using the flexm_setup command/d/vcs501/vcs5.0.1A/bin/vcs -Mupdate -RI -l vcs_sim.log/d/lmgqa2/install/lmc_home/models/mpc860_fx/mpc860_fx02009/examples/verilog/mpc860_tst.v+incdir+/d/lmgqa2/install/lmc_home/models/mpc860_fx/mpc860_fx02009/src/verilog +libext+.inc/d/lmgqa2/install/lmc_home/models/mpc860_fx/mpc860_fx02009/examples/verilog/mpc860.v/d/lmgqa2/install/lmc_home/models/mpc860_fx/mpc860_fx02009/examples/verilog/mpc860_fx_vcs.v /d/lmgqa2/install/lmc_home/lib/hp700.lib/slm_pli.o -P/d/lmgqa2/install/lmc_home/sim/pli/src/slm_pli.tab -lmc-swift+incdir+/d/lmgqa2/install/lmc_home/sim/pli/srcUsing DesignWare Memory <strong>Models</strong> with VCSDesignWare Memory <strong>Models</strong> (DWMM) are SWIFT-compatible binary simulationmodels that have the extension “_mx” (<strong>for</strong> example, model_mx.) To use DWMMmodels with VCS, follow these steps:1. Make sure VCS is set up properly and all required environment variables are set, asexplained in “Setting Environment Variables” on page 40.2. If you are using DWMM testbench commands in your design, add the followingline to your Verilog testbench:`include "mempro_pkg.v"For in<strong>for</strong>mation on using the DWMM testbench commands, refer to the DesignWareMemory Model User’s Manual.3. Generate Verilog wrapper files <strong>for</strong> the model, as shown in the following example:% $LMC_HOME/bin/vcs_sg -t -lc -m model_mxOctober 6, 2003 <strong>Synopsys</strong>, Inc. 53

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