Simulator Configuration Guide for Synopsys Models

Chapter 1: Using Synopsys Models with SimulatorsSimulator Configuration GuideVHDL Example InstantiationU0: cy62128_mxGENERIC MAP(DefaultData => "11111111",DelayRange => "Max",MemoryFile => "mem.dat",MessageLevel => "15",ModelAlias => "TB_CMD_TEST",ModelConfig => "x\0000 0000\",ModelId => "99999",TimingVersion => "55")PORT MAP(a => a,ce1_n => ce1_n,ce2 => ce2,io => io,oe_n => oe_n,we_n => we_n);NoteThe ModelConfig values in model wrappers for both VHDL and Verilog aregenerated in Verilog format by default (for example, “32’h0” in the abovemodel instantiation). You can change this value to any valid 32-bit vector ina quoted string, as explained in Table 5.Verilog Example Instantiationcy62128_mx model1(.a ( a ),.ce1_n ( ce1_n ),.ce2 ( ce2 ),.io ( io ),.oe_n ( oe_n ),.we_n ( we_n ) )defparammodel1.DefaultData = "8'b11111111",model1.DelayRange = "Max",model1.MemoryFile = "mem.dat",model1.MessageLevel = "15",model1.ModelAlias = "TB_CMD_TEST",model1.ModelConfig = "32'h0",model1.ModelId = "99999",model1.TimingVersion = "55" ;34 Synopsys, Inc. October 6, 2003