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Simulator Configuration Guide for Synopsys Models

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<strong>Simulator</strong> <strong>Configuration</strong> <strong>Guide</strong>Chapter 1: Using <strong>Synopsys</strong> <strong>Models</strong> with <strong>Simulator</strong>sTable 5: DesignWare Memory Model SWIFT Parameters (Continued)Parameter Usage Valid Values, Examples, &DefaultsModelConfigUse this parameter to set values in a 32-bitcontrol word that configures variousaspects of model operation, such as theoptional power-on sequence in SDRAMdevices.Valid values are 32-bit vectors inquoted strings represented as binary(b), decimal (d), hexadecimal (h), oroctal (o). Valid <strong>for</strong>mats are VHDLand Verilog.Example: “32’hffffffff” (Verilog)Example: X“ffffffff” (VHDL)Default: Model-specific. See theindividual model datasheets <strong>for</strong>in<strong>for</strong>mation on what each bit in thecontrol word represents in terms ofmodel operation.Instantiating DesignWare Memory <strong>Models</strong>First, generate a model wrapper file, as explained in the chapter <strong>for</strong> your simulator inthis manual. The model wrapper is a .v or .vhd file that contains most of the in<strong>for</strong>mationneeded to instantiate the model. You must compile this file in with your simulatorexecutable, but values you set in your model instantiation in the testbench overridecorresponding values set in the model wrapper file. In other words, the model wrapperfile and model instantiation are two different things that happen to contain overlappingin<strong>for</strong>mation.Then, instantiate the model in your testbench. For example, in your model instantiationin the testbench, you must map the model’s ports to signals in your design, and modifySWIFT parameters as needed (see Table 5 <strong>for</strong> valid values and examples). Here aresome VHDL and Verilog instantiation examples <strong>for</strong> a Designware Memory Model. Notethe _mx extension that is present in the model name <strong>for</strong> all DesignWare Memory<strong>Models</strong>.HintFor model-specific instantiation examples that include correct port namesand default values <strong>for</strong> the required SWIFT parameters, see the individualmodel datasheets.You can cut-and-paste the model instantiation right out ofthe model datasheet and drop it into your testbench. You can access thecorrect model datasheet <strong>for</strong> the version of the model that you are using withthe sl_browser tool ($LMC_HOME/bin/sl_browser).October 6, 2003 <strong>Synopsys</strong>, Inc. 33

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