Simulator Configuration Guide for Synopsys Models

Chapter 1: Using Synopsys Models with SimulatorsSimulator Configuration GuideTable 5: DesignWare Memory Model SWIFT Parameters (Continued)Parameter Usage Valid Values, Examples, &DefaultsDefaultDataUse this parameter to specify the defaultvalues for uninitialized memory addressesfor a model instance. These are the defaultvalues that are used for the memory if youdon’t preload the model using aMemoryFile.If you don’t specify a memory width equalto the width of the model’s memory, themodel loads the right-most bits in each rowof memory with the specified values andleft fills the unspecified memory locationswith zeros.Benefit: Using the DefaultData parameterallows you to specify memory contentswithout consuming any workstationmemory during simulation.Valid values: Bit vectors in quotedcharacter strings represented asbinary (b), decimal (d), hexadecimal(h), X, or octal (o).Valid formats:– Verilog: ’[b|o|d|h]– VHDL: [b|o|x]“”The default radix for VHDL isbinary. VHDL values can includeunderscore characters to improvereadability.Examples:Note: DefaultData values must bepresented as strings (insidequotation marks).– Hexadecimal values:– “8’h5f” (Verilog)– “x\”5f\”” (VHDL —backslashes are needed toescape the double quotes)– Binary values:– “8’b01011111” (Verilog)– “01011111” (VHDL — defaultradix is binary)– “0101_1111” (VHDL)– Octal values:– “8’o137” (Verilog)– “o\”137\”” (VHDL)Default: Model-specific — seemodel wrapper file.If you omit DefaultData, the valueused will be set inside the modelwrapper file.Note: Some memory models settheir memories to all 1s or someother value. When you set theDefaultData parameter, youoverride those settings.32 Synopsys, Inc. October 6, 2003