Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuideIndexVVariableslocation map, Mentor Graphics 126vcom command 78, 81, 84, 247VCSFlexModel examples run script 51invoking on AIX 43invoking on HP-UX 42invoking on Linux 43invoking on Solaris 42with custom memory models 286with DesignWare Memory Models 53with FlexModels 44with hardware models 55with SmartModels 42with VERA 215VCS utilitieswith hardware models 58VCS_HOME environment variable 41VCS_LMC environment variable 55VCS_LMC_HM_ARCH environmentvariable 55vcs_sg script 53VCS_SWIFT_NOTES environmentvariable 41Vectors, test, logging 182VEDA Vulcanwith hardware models 38VERAcompiling source files 213compiling testbench 214testbench creation 210testbench example 211UDF interface 208with custom memory models 299with DesignWare Memory Models 223with FlexModels 207with FlexModels in testbench 211with VCS 215VERA command 214Veriloginclude pkgs 64slm_pli.o 27VHDL genericsLMSI_DELAY_TYPE 203LMSI_LOG 203LMSI_TIMING_MEASUREMENT 203with Scirocco 202vhdlan command 197, 293ViewLogic Fusionwith hardware models 38vlib command 78, 83, 246vmap command 83, 246vsg script 67, 83, 95, 246, 249, 256vsim command 78, 81, 84, 247V-System 79vsystem.ini file 80WWindowsSmartModel, tracing instructionexecution 142SmartModels, how they work 141SmartModels, with QuickSim II 141Word triggeringsetting 142WrappersSWIFT 93October 6, 2003 Synopsys, Inc. 311