Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuideIndexNncshell command 109, 115, 251ncshell file 112ncsim command 110, 119ncsim file 114NC-Verilogsimulating with LMTV 91with DesignWare Memory Models 95with hardware models 97with MemPro models 97with SmartModels 91ncverilog command 97NC-VHDLwith custom memory models 296with DesignWare Memory Models 114with FlexModels 110with SmartModels 109ncvhdl command 110, 115, 251nologvectors signal instance command 182PParameterMessageLevel 31Parametersalso called attributes 19, 29DefaultData 32DelayRange 23, 30FlexCFile 24FlexModelId 23FlexModelSrc 24FlexTimingMode 23MemoryFile 31ModelAlias 30ModelConfig 33ModelId 29TimingVersion 23, 30PCLFile property 130, 154PIN property 130, 146, 155Pin symbols 128pin_map file 146, 147example 148PIN_NAME mapping 146PIN_NAME property 131, 146, 156PIN_NO property 131Pinsmapping 147mapping, conditional 149PINTYPE property 130, 155PKG property 131PLIdynamic linking with custom memorymodels 290dynamic linking with FlexModels 63dynamic linking with Hardware models97dynamic linking with MemPro models 97dynamic linking with SmartModels 61static linking with DesignWare MemoryModels 66static linking with FlexModels 289static linking with SmartModels 63PLIWizard 268propagation command 180PropertiesCOMP 131, 156editing 139, 162JEDECFile 130, 154MemoryFile 129, 154MODEL 130, 155, 167PCLFile 130, 154PIN 130, 146, 155PIN_NAME 131, 146, 156PIN_NO 131PINTYPE 130, 155PKG 131REF 131, 156SCFFile 154SWIFT 145, 163SWIFT_TEMPLATE 130, 155symbol 128symbol, required for simulation 130, 155TimingVersion 129, 153October 6, 2003 Synopsys, Inc. 307