Simulator Configuration Guide for Synopsys Models

IndexSimulator Configuration GuideLogging test vectors 182Logic simulation 134, 158with SmartModels 134, 158Loop mode, with hardware models inQuickSim II 183MMappingindeterminate strength 181pin 147PIN_NAME 146pins, conditional 149unknowns 180Measurement, timing 182Memory image formats$readmemh 31MIF 31MemoryFile parameter 31MemoryFile property 129, 154MemPro modelsdynamic linking with PLI 97with NC-Verilog 97Mentor Graphicsanalysis tools 167design environment 167location map variables 126user tree management 125MessageLevel parameter 31Messagescustom memory models 283custom memory models, constants 284custom memory models, controlling 284DesignWare Memory Models 31SmartModel error 139SmartModel format 139SmartModel note 139SmartModel trace 139SmartModel warning 139MGC component interface 167MODEL property 130, 155model.vhd 64, 80model.vhd file 93model_fx_comp.vhd 80model_fx_sim.vhd 64, 80model_fx_sim.vhd file 93model_mx.v file 67, 95, 96, 249, 256model_mx.vhd file 83, 115, 246, 251model_mx_bus.v file 54model_mx_bw.vhd file 83, 247model_mx_comp.vdh file 115, 251model_pkg.o 27model_pkg.vhd 80model_tst.vhd 64, 80model_tst.vhd file 93model_user_pkg.vhd 80ModelAccessfor QuickSim II 164ModelAccess for QuickSim IIversion number 164ModelAlias parameter 30ModelConfig parameter 33ModelId parameter 29modelsim.ini file 80MTI Verilogsimulating using LMTV 61with custom memory models 290with DesignWare Memory Models 66with FlexModels 63with Hardware models 68MTI VHDLwith custom memory models 294with DesignWare Memory Models 82with FlexModels 79with hardware models 84with SmartModels 75306 Synopsys, Inc. October 6, 2003