Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuideIndexDDeclarations, variable 174DefaultData parameter 32Delay files 174DelayRange 23DelayRange parameter 30Delays, propagation 174Descriptionsfunctional 167, 169graphical 167, 169technology 169timing 169Descriptors, determining for hardwaremodels 168Design ArchitectSmartModel library menus to 126with SmartModels 126Design Architect menusbuilding designs with SmartModels 131,156levels 132system 132Design environment, MGC 167Designsbuilding, using menus 131, 156building, without menus 133, 157DesignWare Memory Modelsfunction-only operation 30instantiating 33messages 31PLI static linking 66with MTI Verilog 66with MTI VHDL 82with NC-Verilog 95with NC-VHDL 114with QuickSim II 151with Scirocco 199with SystemC 261with VCS 53with VERA 223Drive strengths 135, 158DWMM 151, 152Eentities.vhd file 200, 259Environment variablesAMPLE_PATH 126CDS_INST_DIR 90LD_LIBRARY_PATH 40, 41, 60, 74,90, 91, 108, 124LM_DIR 40, 60, 74LM_LIB 40, 60, 74LM_LICENSE_FILE 40, 60, 74, 90,108, 123, 192, 261LMC_SFI 55LMC_TIMEUNIT 110, 114, 119SHLIB_PATH 41, 60, 75, 91, 108, 124SNPSLMD_LICENSE_FILE 40, 60, 74,90, 108, 123, 192, 261SSI_LIB_FILES 213SYNOPSYS_SIM 192VCS_HOME 41VCS_LMC 55VCS_LMC_HM_ARCH 55VCS_SWIFT_NOTES 41Errorsmessages 139registration 172Evaluationhardware models in QuickSim II 179ExamplesFlexModel VHDL instantiation 45, 64,81, 94, 198FlexModels with VCS 48FFault simulationwith SmartModels 22Filescds.lib 92, 94, 96, 111, 114, 250, 257,289components.vhd 200, 259delay (.DLY) 174entities.vhd 200, 259October 6, 2003 Synopsys, Inc. 303