Simulator Configuration Guide for Synopsys Models

IndexSimulator Configuration Guide$lm_timing_information 101$lm_timing_measurements 102$lm_unknowns 103add breakpoint 142add bus 143add lists 141, 143add monitors 141add primitive 134add synonym 143add traces 141command channel 21create_smartmodel_lib 194, 199, 258flexm_setup 25force 142lm_disable_timing_checks 121lm_enable_timing_checks 121lm_loop_instance 121lm_model 166, 169, 171, 172, 174, 176lm_model, syntax 185lm_pam_shortage 121lm_pattern_history 122lm_timing_measurements 121lm_unknowns 121lm_vconfig 105lmsi list 202lmsi logon 202lmsvg 105LMTV 267lmvc_template 56ncelab 92, 95, 97, 113, 257, 290ncshell 109, 115, 251ncsim 92, 95, 97, 110, 119, 257, 290ncverilog 97ncvhdl 110, 115, 251ncvlog 92, 95, 97, 257, 290nologvectors signal instance 182propagation 180reg_model 145, 169, 176scsg 262, 264scsim 200, 259signal instance 137, 160, 177, 182, 183,185simv 55, 217sm_entity 76, 79, 82, 246tmg_to_ts 169tmg_to_ts, syntax 188unknown handling 180vcom 78, 81, 84, 247VERA 214vhdlan 197, 293vlib 78, 83, 246vmap 83, 246vsim 78, 81, 84, 247COMP property 131, 156Compiling C filesAIX 28HP-UX 27Linux 29Solaris 27Component interface 169Component registration 145components.vhd file 200, 259C-only Command Modecompiling C files 27with FlexModels 26Constraint mode switch 136Conversionsshell software 174technology file 174Convertertmg_to_ts 169create_smartmodel_lib command 194,199, 258Custom memory modelscontrolling message output 284dynamic linking with PLI 290instantiating 285message level constants 284messages 283with MTI Verilog 290with MTI VHDL 294with NC-VHDL 296with Scirocco 292with VCS 286with VERA 299with Verilog simulators 283with VHDL simulators 283Custom symbols 144, 163mapping 146302 Synopsys, Inc. October 6, 2003