Simulator Configuration Guide for Synopsys Models

Appendix B: Using Custom Memory ModelsSimulator Configuration Guide4. Create the logical-to-physical mapping for the slm_lib and work libraries by addingthe following lines to your cds.lib file:define slm_lib ./slm_libdefine work ./work5. Compile the DWMM VHDL files into your slm_lib library:% ncvhdl -w slm_lib $LMC_HOME/sim/ncvhdl/src/slm_hdlc.vhd% ncvhdl -w slm_lib $LMC_HOME/sim/ncvhdl/src/mempro_pkg.vhd6. After generating a custom memory model, compile the VHDL code for the modelinto your work library, as shown in the following example:% ncvhdl -w work mymem.vhd7. Add LIBRARY and USE statements for the slm_lib within your testbench code:LIBRARY SLM_LIB;USE SLM_LIB.mempro_pkg.all;This also provides access to DWMM testbench commands.For more information on using the DWMM testbench interfaces, refer to the “HDLTestbench Interface” chapter in the DesignWare Memory Model User’s Manual.8. Instantiate your custom memory models in your testbench. Define ports andgenerics as required. For information on generics, see “Instantiating CustomMemory Models” on page 285. For information on message levels and messagelevel constants, see “Controlling Messages” on page 283.9. Compile your testbench into your work library as shown in the following example:% ncvhdl -w work testbench.vhd10. Elaborate your design as shown in the following example:% ncelab testbench_configuration11. Invoke the NC-VHDL simulator as shown in the following example:% ncsim testbench_configuration298 Synopsys, Inc. October 6, 2003