Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuideAppendix B: Using Custom Memory Models7. After generating a custom memory model, compile the VHDL code for the modelinto your work library, as shown in the following example:% vcom -93 -work work mymem.vhd8. Add LIBRARY and USE statements for the slm_lib to your testbench code:LIBRARY SLM_LIB;USE SLM_LIB.mempro_pkg.all;This also provides access to DWMM testbench commands.For more information on using the DWMM testbench interfaces, refer to the “HDLTestbench Interface” chapter in the DesignWare Memory Model User’s Manual.9. Instantiate your custom memory models in your testbench. Define ports andgenerics as required. For information on generics used with custom memorymodels, refer to “Instantiating Custom Memory Models” on page 285. Forinformation on message levels and message level constants, refer to “ControllingMessages” on page 283.10. Compile your testbench into your work library as shown in the following example:% vcom -work work testbench.vhd11. Invoke the simulator on your testbench as shown in the following example:% vsim testbenchOctober 6, 2003 Synopsys, Inc. 295