Simulator Configuration Guide for Synopsys Models

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Appendix B: Using Custom Memory ModelsSimulator Configuration GuideUsing Custom Memory Models withMTI VHDLTo use custom memory models with MTI VHDL, follow this procedure:1. Make sure MTI VHDL is set up properly and all required environment variables areset, as explained in “Setting Environment Variables” on page 73.2. Append the shared library location to the library search path environment variablesetting.❍❍Solaris or Linux:% setenv LD_LIBRARY_PATH \$LMC_HOME/lib/platform.lib:$LD_LIBRARY_PATHwhere platform is sun4Solaris or x86_linuxHP-UX:% setenv SHLIB_PATH \$LMC_HOME/lib/hp700.lib:$SHLIB_PATH3. Create slm_lib and work directories:% vlib ./slm_lib% vlib ./work4. Create the logical to physical mapping for the slm_lib and work libraries:% vmap slm_lib ./slm_lib% vmap work ./workThis step also creates a modelsim.ini file in the current working directory.5. Open the modelsim.ini file in a text editor, and edit the line for Resolution, as shownin the following example:Resolution = 100ps6. Compile the DWMM VHDL files into your slm_lib library:% vcom -93 -work slm_lib $LMC_HOME/sim/mti/src/slm_hdlc.vhd% vcom -93 -work slm_lib $LMC_HOME/sim/mti/src/mempro_pkg.vhd294 Synopsys, Inc. October 6, 2003
Simulator Configuration GuideAppendix B: Using Custom Memory Models7. After generating a custom memory model, compile the VHDL code for the modelinto your work library, as shown in the following example:% vcom -93 -work work mymem.vhd8. Add LIBRARY and USE statements for the slm_lib to your testbench code:LIBRARY SLM_LIB;USE SLM_LIB.mempro_pkg.all;This also provides access to DWMM testbench commands.For more information on using the DWMM testbench interfaces, refer to the “HDLTestbench Interface” chapter in the DesignWare Memory Model User’s Manual.9. Instantiate your custom memory models in your testbench. Define ports andgenerics as required. For information on generics used with custom memorymodels, refer to “Instantiating Custom Memory Models” on page 285. Forinformation on message levels and message level constants, refer to “ControllingMessages” on page 283.10. Compile your testbench into your work library as shown in the following example:% vcom -work work testbench.vhd11. Invoke the simulator on your testbench as shown in the following example:% vsim testbenchOctober 6, 2003 Synopsys, Inc. 295
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Simulator ConfigurationGuide for Sy
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PrefaceSimulator Configuration Guid
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Chapter 1: Using Synopsys Models wi
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Chapter 2: Using VCS with Synopsys
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Chapter 3: Using ModelSim Verilog w
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Chapter 4: Using ModelSim VHDL with
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Chapter 5: Using NC-Verilog with Sy
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Chapter 6: Using NC-VHDL with Synop
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Chapter 7: Using QuickSim II with S
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Chapter 8: Using Scirocco with Syno
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Chapter 9: Using VERA with Synopsys
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Simulator Configuration Guide for Synopsys Models

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