Simulator Configuration Guide for Synopsys Models

Simulator Configuration GuideAppendix B: Using Custom Memory Models7. Compile the DWMM VHDL files into your slm_lib library:NoteThese examples provide details for event-based simulation. For informationon cycle-based operation, see the Scirocco Reference Manual.% vhdlan -w slm_lib $LMC_HOME/sim/vhpi/src/slm_hdlc.vhd% vhdlan -w slm_lib $LMC_HOME/sim/vhpi/src/mempro_pkg.vhdCautionDo not use the Scirocco -noevent switch when compiling the slm_hdlc.vhdpackage. This can cause the package to compile incorrectly.8. After generating a custom memory model, compile the VHDL code for the modelinto your work library, as shown in the following example:% vhdlan mymem.vhd9. Add slm_lib LIBRARY and USE statements to your testbench:LIBRARY SLM_LIB;USE SLM_LIB.mempro_pkg.all;This also provides access to DWMM testbench commands.For more information on using the DWMM testbench interfaces, refer to the “HDLTestbench Interface” chapter in the DesignWare Memory Model User’s Manual.10. Instantiate your custom memory models in your design. Define ports and genericsas required. For details, see “Instantiating Custom Memory Models” on page 285.For information on message levels and message level constants, refer to“Controlling Messages” on page 283.11. Compile your testbench as shown in the following example% vhdlan testbench.vhd12. Invoke the Scirocco simulator as shown in the following examples:❍If you are using Scirocco 2001.10 or later:% scs testbench_configuration% scsim -vhpi slm_vhpi:foreignINITelab:cpipe❍ If you are using Scirocco 2000.12:% scsim -vhpi slm_vhpi:foreignINITelab:cpipe testbench_configurationOctober 6, 2003 Synopsys, Inc. 293